i have some problem about current time in vhdl

Question

I am the first student to start vhdl recently. It is currently working on the FPGA board. I wish my seven-segment would have the current time whenever I pressed the RESET button. Is there a way to solve it?

I searched stackoverflow all day. but i can not find solution..

  -- Time information
  constant HOUR_INT   : integer                       := 00;  --  I think we should put the current time in here.
  constant HOUR_HEX   : std_logic_vector(7 downto 0)  := X"00";
  constant MINUTE_INT : integer                       := 00;
  constant MINUTE_HEX : std_logic_vector(7 downto 0)  := X"00";

if reset = '0' then
      hour <= conv_std_logic_vector(datetime.hour_int, 5)

in this code proportion, why i have to input 5 next to hout_int?

It's depending on what you call the current time. You can create a time counter but you have to initialize the time with something. I need more informations on your system to help you. Does your FPGA have an internet connection ? — Gautitho, Jun 07 '19 at 08:27

score 1 · Answer 1 · answered Jun 07 '19 at 10:13

In HDL you can only keep track of the elapsed time, using some counters running from an external reference: a clock signal with a known frequency.

You always have to set the current date/time by initializing¹ your counter registers. Setting the time/date is normally done through a CPU interface. Which implies you need a CPU which gets the time from somewhere (A real-time clock or a connection to the outside world) and then writes the time in some format to your registers.

¹_{Even if your FPGA has battery backup: it always has to be set at least the first time.}

Joost · Accepted Answer · 2019-06-07T09:58:01.050

0

I think it isn't possible to get the current time of the system (considering the attempts / questions of other people on this forum). So it's also impossible to use reset for get the current time.

Maybe it's usefull to take a look here

someone who has already tried it in a different way with an RTC (with success): - here non-manually set clock - here manually set clock

edited Jun 07 '19 at 09:58

answered Jun 07 '19 at 08:28

Joost

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Thank you for your answer! Is it possible to set the time when uploading the program on the fgpa board? – 박준수 Jun 07 '19 at 08:32
No it's not possible but you can start to count time from 0 at the start of the FPGA. – Gautitho Jun 07 '19 at 08:38
I found another website where someone tries it with an RTC module (Real Time Clock). Take a look here: [link](http://jimmy-embedded-c-n-vhdl.blogspot.com/2010/09/synthesizable-rtc-in-vhdl-coming-soon.html) I think it is possible to give the current time in the execution, but I don't know how to do that (at this moment). I would have to figure out that. – Joost Jun 07 '19 at 08:45
@Gautitho, I thought about that too. maybe you can make a clock with the current time through the internal clock. – Joost Jun 07 '19 at 08:49
@Joost you mean, when fpga including rtc, i can upload my current time. right? sorry, my english skill is terrible :( – 박준수 Jun 07 '19 at 09:41
Yes that's what I mean. Did you follow the link I had send to you? I saw another link. In this link it's possible to set time manualy [here](http://jimmy-embedded-c-n-vhdl.blogspot.com/2011/01/rtc-on-fpga-with-manual-set.html) – Joost Jun 07 '19 at 09:54

i have some problem about current time in vhdl

2 Answers2