-1

I'm having a hard time understanding the way flip-flops actually flip states and wondering why is it such a design commonly used, when simpler design could suffice, from my current opinion.

I'm hoping that after showing you my version of a latch diagram, someone could point out the flaws and that may help me understand why a flip-flop latch is better.

I was reading a book and bumped into some "general" form of latch: https://i.stack.imgur.com/jQAs8.png (sorry, I don't have the reputation insert images)

I've been on it for about 2 hours trying to truly grasp the mechanism. Seeing that I can't do it, I've draw my version of a latch:

https://i.stack.imgur.com/I8J5s.png

The blue diagram, the one from the book, is harder to follow because some gates will switch 2 times when the inputs switches once, because as the output is tunneled back as input to the same gate, the output may change base on its previous value.

My version of the diagram, the one in black, uses a more programmable approach. I take the current state C and decide if it differs from the input state and output it into A. I use A value in an AND gate with the enable wire to decide if both criteria is met and put it in B. Finally, I'm using a XOR to change the state and output as C.

I'm hoping someone can tell me why is this bad, what I haven't taken into consideration or why a more complex mechanism is needed.

Thank you in anticipation.

Abscon Ditus
  • 1
  • 1

1 Answers1

0

As far as I can tell, your latch implementation should work.

However, there is more to low-level digital design than just gate count. In actual circuits, not all gates are created equal as the actual implementation of these gates can make some more "costly" than others (usually measured in area/transistor count and complexity in routing). For typical CMOS implementations, NAND gates are really cheap (only 4 transistors for two input NAND) so alot of primitives use NAND (or NOR) as a building block for more complex designs. XOR is generally a more complicated gate to implement, most CMOS implementations Ive seen use 8 transistors. Without going through and optimizing your design, it might take at least 20 or more transistors to implement while the latch design from the textbook only takes 16 (A 20%+ savings in area per bit stored, which is quite significant). There is alot more at play here than just transistor count as well; things like transistor sizing, routing and trace sizing, power considerations and glitch protection when actually going through and implementing designs, so even this simple analysis is incomplete and might be missing reasons for the textbook implementation vs yours (or vice versa).

Asynchronous sequential logic (which is what latch/flipflop implementations are) can be difficult to understand which is why most circuits use higher-level constructs and treat these details as black boxes (and it also creates a nice abstraction where the actual implementation doesnt matter so long as the properties of that element are preserved).

Unn
  • 4,775
  • 18
  • 30