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There's something that confuses me, in Computer System Architecture(Morris Mano), Chapter 5, the book uses a simple microprocessor which has the following instruction cycle:

e.g. LDA Operation:

AR<---PC (T0)

IR<---M[AR] (T1)

PC<---PC+1 (T1)

Decode (T2)

DR<---M[AR] (T3)

AC<---DR (T4)

I'm having a hard time understanding this cycle and why it isn't like this:

MAR<--PC(T0)

MBR<---M(MAR](T1)

Decode(IR<---MBR)(T2)

MBR<--M(MAR](T3)

AC<---MBR(T4)

My questions are:

Why isn't MBR and MAR notation used in the book and how can "read from memory" and "write to IR" operations be done at the same since write operation requires the result of read operation?

azkabantutsagi666
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    I'm voting to close this question as off-topic because it is not a practical programming question. It is a computer architecture question (about a hypothetical architecture, at that). – Raymond Chen Dec 19 '18 at 15:37

1 Answers1

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There are no MBR or MAR registers, there are only the following registers in the design (ignoring the interrupt and IO functions):

AR -- Address register; used to address memory

PC -- Program counter; address of the instruction being executed

DR -- Data register; temporary storage of data

AC -- Accumulator; result of any ALU operation ends up in this register

IR -- Instruction register; storage of the current instruction opcode

E -- Flag register from ALU operations

SC -- Sequence counter; used to determine which step of the instruction is being done

Flowing through the LDA instruction for example:

T0: AR <- PC // Put the Program counter into the Address register so we can get the instruction; only the Address regsiter can access memory

T1: IR <- M[AR], PC <- PC + 1 // M[AR] means access memory (M) at address stored in AR ([AR]), and in this case put that value at address AR into the Instruction register; at the same time increment the Program counter which can be done in parallel as the increment can be done without using the bus

T2: Decode(IR); AR <- IR(0-11) // Now the instruction is decoded; during this time the address argument of the instruction is pass into the Address register

T3: DR <- M[AR] // Once weve determined in T2 that this is a LDA, we need to do the steps involved; the goal being to take the word from memory and get it into AC. To do this, we first need to read it out of memory, thus the M[AR], read memory at address AR (which is from the instruction became of the transfer we did in T2). We want to put it into AC, but since AC cannot be loaded from the bus directly, we need to put it somewhere else first, somewhere it can be then transferred to AC, thus put it in DR

T4: AC <- DR; SC <- 0 // Now that the data is in DR, we can move it via the ALU into AC; note that the ALU doesnt actually do any work on the data in the case of the LDA, it just passes the data through. Now that the instruction is done, reset the Sequence counter to 0
Unn
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  • Thank you very much for your answer! But I have two questions: 1. How is (memory-read) operation and (write to IR operation) done at the same time? Because one uses data bus while the other one uses adress bus, they don't conflict? 2. So the DR is just a register to keep temporary data because IR can not store two values at the same time? So this means all of the data which will be fetched during the incoming cycles(let's say T5,T6,T7......) will be stored in DR and DR will be overwritten right? Thanks in advance. – azkabantutsagi666 Dec 20 '18 at 14:52
  • 1) The bus is this system is the data lines that connect alot of these registers together as well as memory. See the diagram near the beginning of the chapter, the address lines from `AR` to memory go directly to that module while the bus goes to most of the registers and memory. So long as there is only one driver of the bus, it's fine; in this case only memory is driving the bus. 2) Basically yes, though the IR also drives the control signals in system so if would mess everything up to store data there. And yes, DR might be written to multiple times during a single instruction. – Unn Dec 20 '18 at 16:45