In class the professor said that students shouldn't say that they learned to program in Verilog. He said something like Verilog isn't used to program it's used to design. So how is Verilog different from other programming languages?
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1read wiki page: http://en.wikipedia.org/wiki/Verilog – Anycorn Feb 25 '11 at 19:27
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@nodeninja, Verilog is like [this language](https://www.google.com/search?q=electronic+diagrams&tbm=isch) and [this language](https://www.google.com/search?q=lego+diagrams&tbm=isch), except instead of using diagrams, you use "alphanumeric" characters. – Pacerier Apr 10 '17 at 02:20
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Verilog, just like VHDL, is meant to describe hardware. Instead, programming languages such as C or C++ provide a high level description of software programs, that is, a series of instructions that a microprocessor executes.
In practice, Verilog and VHDL do not offer the same features as programming languages, even though they look very much alike. For instance, a for loop in C/C++ describes the sequential execution of a given snippet of code; instead, a for ... generate loop in Verilog/VHDL describes multiple parallel instances of a same hardware building block (say, a AND logic gate). To be precise, there also exists a plain for loop in Verilog, but again, it has to be "synthesizable", that is, the compiler must be able to generate logic that fits the description.
Typically, a beginner in Verilog/VHDL will be tempted to "translate" a given function/algorithm from a C/C++ type of pseudocode directly to Verilog/VHDL: surprisingly, it might sometimes work, but it always lead to dramatically poor design. One must really be aware of these differences in order to become a good Verilog/VHDL programmer.
Greg
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1Your description of the regular Verilog/VHDL `for` loop is incorrect. It is just as sequential as the C/C++ counterpart. The "parallel" version is a `for .. generate`. – Jan Decaluwe Feb 26 '11 at 08:04
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It was indeed inaccurate: I modified my answer according to your comment. My point was that most often the type of `for` loops you write in C/C++ cannot be readily translated into Verilog/VHDL. You need to keep in mind the type of hardware that will be generated (and for loops can generate a real mess) – Greg Feb 26 '11 at 15:14
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2The implied sequence in a for loop may create multiple levels of logic. That may a bad solution for timing, but a good solution for area. Moreover, depending on the case, logic synthesis may do an outstanding job of creating good logic even from an initially non-optimal structure. In other words, a hardware designer has to "understand his compiler" (synthesis tool). But isn't this exactly what good programmers do? – Jan Decaluwe Feb 26 '11 at 17:33
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@Jan: +1, that's a very good point. Still, I think hardware designers need to be even more aware of what their compiler will do than software programmers. – Greg Feb 26 '11 at 17:42
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Verilog is a hardware definition language. Programming languages are generally understood to be languages for telling existing hardware what to do, not for reconfiguring said hardware.
nmichaels
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Because it is an HDL, so it is to define hardware, and anything done in verilog (not really anything, but synthesizable things) will be synthesized into actual hardware. So you can't just use programming features like class and OOPS concept because it can't create any hardware.
But in C, everything will be converted into executable hex file, which will be loaded in your ram while executing the program.
Another basic difference is everything in hardware is concurrent, so if you have written a=b+1 and c=d+1 in verilog, then in the synthesized hardware, both modules will work simaltaneously. But in C everything is sequential, so in same C program actually both instruction will be loaded one by one in your processor.
Karan Shah
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It is a programming language, not to program software, but to describe hardware design - but the output is not necessarily an "application" as we understand it.
The language has a formal syntax.
Robin Green
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Max
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I don't know anything about Verilog but just did a quick googling and the wiki pages seem to do a pretty good job of explaining the differences in concept that your teacher seemed to be eluding to. As some of the other posters here wrote I don't know that I would dismiss this as not a programming language, I think there's a high tendency for programmers to believe if it isn't somehow application programming or assembly programming then it's not really programming, but in short that's BS. Everything above machine code is basically the same to me, if it's a file I give to a computer and it tells the computer how to do something it's programming the computer (I guess the problem is drawing a line between users and developers, we like to feel special). Unless we plan to roll back to punch-cards sometime soon, I think anything that has a C like syntax or allows you to describe in a syntactically strict (well defined) way and modifies the behavior of the computer (what it outputs for a given input) then you've done some programming in one sense or another.
http://dictionary.reference.com/browse/programming
From the wiki page:
http://en.wikipedia.org/wiki/Dataflow_language
Dataflow programming focuses on how things connect, unlike imperative programming, which focuses on how things happen. In imperative programming a program is modeled as a series of operations (thing that "happen"), the flow of data between these operations is of secondary concern to the behavior of the operations themselves. However, dataflow programming models programs as a series of (sometimes interdependent) connections, with the operations between these connections being of secondary importance.
(I think the key here is the qualifiers of the type of programming not that one is a "programming language" and the other is a "design language", from what I understand they're both programming languages they just have distinct purposes and implementations). When I think of design I basically think of this: http://dictionary.reference.com/browse/design and that is not a program although a program may utilize designs (and probably should, generally referred to as design patterns, but not what you're doing)
Linked in from: http://en.wikipedia.org/wiki/Verilog
To your teachers point this language would likely be used to solve different problems from your every day Java/C program, and via a different means, however to say it is not a program seems wrong.
shaunhusain
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Verilog contains features to describe logical netlists(RTL) and features to facilitate simulation of them. Describing an RTL description as a program may convey that one who describes it as such does not throughly understand logic design or synthesis. Describing a testbench stimulus as a program would be appropriate.
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Alternatively, it may convey that such a designer is aware of what logic synthesis really can do, possibly in contrast to his peers who are blinded by a misunderstood "think hardware" paradigm. – Jan Decaluwe Feb 26 '11 at 08:10
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verilog/vhdl is used to create and design specific application system on the chip which embedded into electronic devices.
c/c++ used design softwares on the computer
Allanx
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I am going to tackle this question in a different way. What is a purpose of a programming language? Can the output of a program affect real world and your goals and expectation? If yes then ofcourse verilog is a programming language. Console.log has as much meaning as what it translates to in real world eg. console.log("you have a million unit") has no fiat without authority. So verilog is a programming language in certain sense.
Flood Gravemind
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