syntax error, unexpected '=', expecting IDENTIFIER

Question

I'm creating a sudoku game in verilog(2001) to eventually be put onto an FPGA, I found code for it in java and have been trying to convert it but have run into some errors. Here's the link for the java code www.geeksforgeeks.org/program-sudoku-generator
I have very little verilog experience and am learning as I go.

task automatic removeKDigits()  
    reg count = K; 
    while (count != 0) 
    begin 
        integer cellId = randomGenerator(N*N-1); 

        // System.out.println(cellId); 
        // extract coordinates i  and j 
         i = (cellId/N); 
         j = cellId%9; 

        // System.out.println(i+" "+j); 
        if (mat[i][j] != 0) 
          begin 
            count = count-1; 
            mat[i][j] = 0; 
          end 
       else
          count=count;
    end 
endtask

K is the amount of digits to be removed from the mat[i][j] board, N=9 since its a 9x9 sudoku board. For the lines containing "count=count-1" and "count=count" I'm getting the error
syntax error, unexpected '=', expecting IDENTIFIER
what does it mean? how do I fix it?

I strongly suggest you read up and have a look at existing Verilog code. You have an abundance of errors in there because you treat Verilog as any other computer language. Using HDL requires a major mental adjustment! — Oldfart, Nov 28 '18 at 21:57
Basically, you have bitten off far more than you can chew. Verilog is for designing hardware; Java is for writing software. The task you are attempting is far far more complex than simply trying to translate one language into another: you are trying to transform software into hardware. — Matthew Taylor, Nov 29 '18 at 07:12

score 1 · Answer 1 · answered Nov 29 '18 at 01:41

Unfortunately, it's unlikely you'll be able to port java code to synthesizable Verilog code, without at least a decent knowledge of the principles behind RTLs (Register transfer languages).

Programming languages like Java are a high level descriptions of some logic, that will get converted into machine instructions, and run on a processor. They operate sequentially, one line at a time, in a particular order.

RTLs on the other hand, describe actual hardware. They tend to operate in parallel, on a trigger, typically a clock. Instead of 'variables', you tend to work with 'registers' representing actual flip flops, and the Verilog programme will describe the transfer of data between these registers.

As for the actual issues with your code, it's impossible to point out the errors, because it simply isn't Verilog. I recommend this answer: https://stackoverflow.com/a/5121853/10719567, for a more eloquent description of the differences between programming languages and RTLs, and why it's not that easy to port between the two.

syntax error, unexpected '=', expecting IDENTIFIER

1 Answers1