Stack Overflow
Stack Overflow

Vinayak Hiremath
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reputation
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  • Bangalore, India
  • Member since November 21 2014
  • 3 profile views
  • Last seen Mar 26 '18 at 09:12

An entry-level FPGA Design Verification Professional, working on RTL Design, verilog & systemverilog HDL coding, Custom IP Creation, BFM Based simulation on Altera specific FPGAs.