Verilog: Changing multiple states in one case statement

Question

Basically I'm trying to display the sum or product of two numbers (inputted using switches on an FPGA) onto a 7-segment display. I know that both my addition and multiplication bits work fine, as I've tested them separately.

I'm having trouble with the LSB though. No matter what it just defaults to F and never changes. I think Verilog doesn't allow me to modify both Cout1 and Cout0 in the same case statement. Is there a workaround for this? See my code, below.

always@*
    if (key1press)
    casex(PrintSum)

        // Hex 1 (MSB)
        // Works!
        5'b0xxxx : Cout1 = 7'b1000000;  //0 if S[4] = 0
        5'b1xxxx : Cout1 = 7'b1111001;  //1 if S[4] = 1

        // Hex 0 (LSB)
        // Doesn't work :(
        5'bx0000 : Cout0 = 7'b1000000;  //0
        ...
        5'bx1111 : Cout0 = 7'b0001110;  //F
        //default  : begin
        //            Cout1 = 7'b1000000;   //0 by default
        //            Cout0 = 7'b1000000;   //0 by default
        //end
    endcase

Thanks in advance everyone :)

score 1 · Accepted Answer · answered Dec 11 '17 at 17:40

In simulations, case statements will execute first match. Everything will match the first two conditions (5'b0xxxx, 5'b1xxxx). If you move these conditions to the end, then they will never be reached as there will be a match in the 5'bx0000 to 5'bx1111 range.

There isn't overlap between the care bits. Therefore, the simplest solution is to split Cout1 and Cout0 into separate constitutional statements:

begin
  if (PrintSum[4]) begin
    Cout1 = 7'b1111001;  //1 if S[4] = 1
  end
  else begin
    Cout1 = 7'b1000000;  //0 if S[4] = 0
  end

  case(PrintSum[3:0])
    4'b0000 : Cout0 = 7'b1000000;  //0
    // ...
    4'b1111 : Cout0 = 7'b0001110;  //F
  endcase
end

Other things to be aware of:

Don't use casex
- Casex vs Casez in Verilog
- read § 4.3 of RTL Coding Styles That Yield Simulation and Synthesis Mismatches for details.
Cout0 and Cout1 are inferred latches (level-sensitive). FPGAs have limited or no support for latches. Plus latches can be glitch prone if not done properly.
- What is inferred latch and how it is created when it is missing else statement in if condition.can anybody explain briefly?
- StackOverflow search result for inferred latch

Thank you, this was all really helpful-and thanks for the extra resources too. I made the decision to swap out casex with casez. — gdagis, Dec 12 '17 at 17:14
You should clock the accept answer icon if this satisfies your question. It will help others with similar questions. — Greg, Dec 14 '17 at 18:56

score 0 · Answer 2 · answered Dec 10 '17 at 23:19

0

the following 2 terms from your case statement cover all possible values of the PrintSum selector. Since they are firs int eh list, no other values would ever be hit there.

    5'b0xxxx : Cout1 = 7'b1000000;  //0 if S[4] = 0
    5'b1xxxx : Cout1 = 7'b1111001;  //1 if S[4] = 1

You need to fix the above to provide meaningful values so that the other terms could execute as well.

you might also rearrange the items like this.

    // Hex 0 (LSB)
    // Doesn't work :(
    5'bx0000 : Cout0 = 7'b1000000;  //0
    ...
    5'bx1111 : Cout0 = 7'b0001110;  //F


   // Hex 1 (MSB)
    // Works!
    5'b0xxxx : Cout1 = 7'b1000000;  //0 if S[4] = 0
    5'b1xxxx : Cout1 = 7'b1111001;  //1 if S[4] = 1

answered Dec 10 '17 at 23:19

Serge

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Wouldn't both scenerios results in one value getting "hit" and ending the case then? (Also I tried switching the two items, no such luck unfortunately) – gdagis Dec 11 '17 at 14:09
it will hit the first matching first. So, if PrintSum has 4 lower bits set to '0000', it will hit the first term. However for '00001' it will match the '0xxxx' term, and for '10001', the '1xxxx'. – Serge Dec 11 '17 at 14:32

Verilog: Changing multiple states in one case statement

2 Answers2