Casex vs Casez in Verilog

Question

what is the difference between casex and casez in Verilog ? I have searched about it and find this sentence :

casez treats all z values in the case alternatives or the case expression as don't cares. All bit positions with z can also represented by ? in that position.

casex treats all x and z values in the case item or the case expression as don't

cares.

for example , what is the difference between first one and second one:

1-

casez (instr)
7'b1zzzzzzz: // arithmetic
7'b01zzzzzz: // load-reg
7'b00zzzzzz: // store-reg
endcase

2-

 casex (instr)
    7'b1zxxxxzz: // arithmetic
    7'b01zzxxxx: // load-reg
    7'b00xxxzzz: // store-reg
    endcase

score 6 · Accepted Answer · answered Dec 19 '15 at 17:32

The Verilog Language Reference Manual (now replaced by the SystemVerilog LRM) explains this in great detail. The key difference is when the case expression instr contains x or z values. Remember that both casex and casez look at both the case item and the case expression for x and z values. We call this a symmetric comparison as don't care values can show up in either place.

So if instr was all x's, none of the items in the casez would match, but ALL of the items in the casex would match, and a simulator would pick the first item. Similarly, if instr were all z's, then ALL items would match. I consider casex a useless construct.

SystemVerilog replaces both statements with a case() inside statement. It uses an asymmetric comparison operator ==? that only treats an x or z in the case item as a don't care.

thanks for your answer.:) "Similarly, if instr were all z's, then ALL items would match." does it happen in both casex and casez?@dave_59 — user76767, Dec 19 '15 at 18:11

Casex vs Casez in Verilog

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