How clock speed of devices determined?

Question

How the hardware designer determined the suitable frequency of the clock for the device to work on? After which he/she created the timing diagram which is then further used for interfacing.

All I need to know what is the mechanism for determining the suitable clock and then creating the timing diagrams. My own logic is first designer creates the device such as microprocessor then give it different instructions and then check the results on different clock rates but this is trial and error method, and is there any specific algorithm to do that?

Answer 1

This is really an Electrical Engineering matter. Ultimately, the speed of devices is determined by a detailed characterization of the design through simulation and testing of the engineering samples.

When devices are actually produced in quantity, it is common for each device to be tested and either rejected if it is out of spec or given a speed grade. This testing often examines things like performance at a variety of temperatures and supply voltages. This process is very conservative

Further, if the demand for a higher speed grade is less than the supply, chips may be labeled at a lower speed grade. Why? Faster versions of a chip often command a higher price and the marketing types don't want to hurt the profit margins on these expensive parts.

Thus it is often possible to get away with a lot over overclocking.

Another possible constraint happens when chips must be used in sets (a chip set if you will). In these cases, the speed of a chip may be constrained by the limitations of another chip in the set.

Answer 2

The process normally starts by considering the target market, performance and power point (for example, in a phone, there is a hard limit to how much power can be dissipated without getting too hot). Simplistically, speed and pipeline depth are inversely related. Adding a pipeline stage permits a higher clock frequency, costs area and costs branch misdirect penalty.

At the microarchitectural level, there are small tradeoffs that can be made to win back a bit of timing in different locations if there is a key device frequency that needs to be met.

There are rule-of-thumb calculations for logic depth, but generally this is an iterative process using the whole design flow and static timing analysis (using expensive, complicated simulation tools).