Verilog Module Instantiation Syntax Clarification

Question

I've been looking at some verilog code and came across something I've never seen before and have not been able to find information about online.

module FA_n_bit(c_out, Sum, A, B, c_in);

parameter    word_size = 4;      // the default size of this n bit adder

input       [word_size-1:0]      A, B;
input                            c_in;

output      [word_size-1:0]       Sum;
output                          c_out;

wire        [word_size-1:0]   c_inner;

// the c_out of the ith 1-bit full aderr is the c_in of the (i+1)th full adder 
FA_one_bit  fullAdder [word_size-1:0](
  {c_out, c_inner[word_size-1:1]},
  Sum, 
  A,
  B,
  {c_inner[word_size-1:1], c_in}
);

endmodule

I understand the parameter syntax, but I am having a hard time understanding what the FA_one_bit fullAdder [word_size-1:0] (...) syntax does.

any help would be greatly appreciated. So far I think that its declaring 4 fullAdders but I get lost at the concatenation of the c_out and c_inner[word_size-1:1].

score 1 · Answer 1 · edited May 23 '17 at 12:23

The FA_one_bit is another module instantiated inside FA_n_bit module. The instance name is fullAdder. Also, [word_size-1:0] indicates that word_size number of instances are created.

In Verilog, when you are instantiating a module, that means you are adding extra hardware to the board. Here, 4 fullAdders are added.

Concatenations are expressed using the brace characters { and }, with commas separating the expressions within. Referring to SystemVerilog LRM IEEE 1800-2012, section 11.4.12:

A concatenation is the result of the joining together of bits resulting from one or more expressions. The concatenation shall be expressed using the brace characters { and }, with commas separating the expressions within.

// if a, b and c are 8-bit numbers, the results has 24 bits
For Example: {a, b[3:0], c, 4'b1001}

Here, {c_out, c_inner[word_size-1:1]} means 1-bit of c_out and word_size-1 bits of c_inner from MSB are concatenated. This shall result in a signal of width word_size.

Yet another example from LRM:

{a, b[3:0], w, 3'b101}
// equivalent to the following
{a, b[3], b[2], b[1], b[0], w, 1'b1, 1'b0, 1'b1}

The MSB of concatenated signal is c_out and MSB-1 position is for c_inner[word_size-1] and LSB of signal is c_inner[1].

For more information on array of instances, refer to Array of modules link. Refer IEEE 1800-2012 section 11.4.12 for concatenation operator.

Verilog Module Instantiation Syntax Clarification

1 Answers1