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this my code for an accumulator:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity akkumulator is
    generic (N : natural:=1);
    port(rst: in bit;
         clk: in bit;
         B : in  natural range 0 to N-1;
         A : out natural range 0 to N-1);
end akkumulator;

architecture verhalten of akkumulator is
begin
    p1: process(rst, clk)
       variable ergebnis : natural range 0 to N-1;
    begin
       if (rst = '1') then
           ergebnis := 0;
       elseif (clk'event and clk = '1') then
           ergebnis := ergebnis + B;
       end if;
       A <= ergebnis;
    end process;
end verhalten;

When i compile i get these error messages:

** Error: C:/Modeltech_pe_edu_10.4a/examples/akkumulator.vhd(20): near "then": (vcom-1576) expecting == or '+' or '-' or '&'.

** Error: C:/Modeltech_pe_edu_10.4a/examples/akkumulator.vhd(25): VHDL Compiler exiting

Why?

Kleini
  • 57
  • 7
  • 1
    elseif /= elsif –  Jan 09 '18 at 15:51
  • I'm dumb. Thank you. – Kleini Jan 09 '18 at 15:53
  • Also see [VHDL Counter Error (vcom-1576)](https://stackoverflow.com/questions/33103363/vhdl-counter-error-vcom-1576). You don't need the use clause making package numeric_std declarations visible, none are used. The search bar search terms used to find this example were *vcom 1576 near then* –  Jan 09 '18 at 17:25

0 Answers0