0

I've been having a problem trying to figure out what "X_MODIFY" from EZ-Kit Lite BF537 (Analog Devices) means, which is part of the DMA's configuration. What exactly does it change? It's the step take after the loop begins?

Here is the code. You guys can find it on the examples sessions of the book Embedded Signal Processing with the Micro Signal Architecture by Woon-Seng Gan and Sen M. Kuo.

*pDMA3_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1 | DMA2D | DI_SEL;
// Start address of data buffer
*pDMA3_START_ADDR = iRxBuffer1;
// DMA loop count
*pDMA3_X_COUNT = 2*INPUT_SIZE;
// DMA loop address increment
*pDMA3_X_MODIFY = 4;
*pDMA3_Y_COUNT = TOTAL_FRAME;
*pDMA3_Y_MODIFY = 4;

I am working with audio frames and may have to use more than two channels in the future, so I would like to understand how the X_MODIFY affects my data.

Thank you very much!

Makyen
  • 31,849
  • 12
  • 86
  • 121
  • Given your specific question, it would be helpful if you included a link to the documentation in which you saw X_MODIFY. We can guess, with a high probability of being correct, but we should not have to. This would allow more people to answer your question with less effort. – Makyen Mar 02 '15 at 13:01
  • Please provide the page number so we do not have to go searching for the code. You are asking for help. Please make it easy for people to give that help to you. – Makyen Mar 04 '15 at 05:19

2 Answers2

0

The X_MODIFY register is explained on page 293 of the book you cite:

The X_COUNT register specifies the number of transfers that are required, and
the X_MODIFY register specifies the number of byte increments after every data
transfer. Note that the data transfer can be 8, 16, or 32 bits. Therefore, X_COUNT
is related to the number of words, and the word can be 8, 16, or 32 bits. However,
X_MODIFY is always expressed in number of bytes. Blackfin processors allow
one-dimensional (1D) and two-dimentional (2D) DMA modes. When the DMAx_
CONFIG register shown in Figure 7.1 is set to operate in 1D mode, only the X_
COUNT and X_MODIFY registers need to be set up. Otherwise, when 2D mode
is set, Y_COUNT and Y_MODIFY registers must also be set up in addition to the
X_COUNT and X_MODIFY registers. The 2D DMA can be considered as a nested
loop, where X_COUNT and X_MODIFY specify the inner look and Y_COUNT
and Y_modify specify the outer loop. The 2D DMA is particularly useful in
implementing double buffers for block processing mode and in addressing 2D data
like images. We show more examples on how to set up 2D DMA in Hands-On
Experiments 7.4 and 7.5.

Given the setup you have provided, each transfer of DMA Channel 3 (Serial Port 0 Receive, SPORT 0 Rx) will be 32 bits and after each transfer (within the inner loop) the memory address will be incremented by 4 bytes (X_MODIFY). It will also be incremented by 4 bytes between each inner loop (Y_MODIFY).

Effectively, what you have provided sets up a couple of loops basically like:

//SETUP DMA
// Config is set to: Memory write | Transfer size = 32 bits | generate interrupt
//                   | autobuffer | 2D DMA mode 
//                   | interrupt is on completion of each X_COUNT loop
DMA3_START_ADDR = iRxBuffer1;
DMA3_X_COUNT = 2*INPUT_SIZE;
DMA3_X_MODIFY = 4;
DMA3_Y_COUNT = TOTAL_FRAME;
DMA3_Y_MODIFY = 4;

//Begin DMA
while (DMA3_CONFIG & DMAEN) { //autobuffer mode
    DMA3_CURR_ADDR = DMA3_START_ADDR;
    for(DMA3_CURR_Y_COUNT = DMA3_Y_COUNT; DMA3_CURR_Y_COUNT > 0; DMA3_CURR_Y_COUNT-- ) {
        for(DMA3_CURR_X_COUNT = DMA3_X_COUNT; DMA3_CURR_X_COUNT > 0; DMA3_CURR_X_COUNT--){
            //Transfer data from serial port 0 to memory at location DMA3_CURR_ADDR.
            //  Note that here is actually the hardware waiting for an interrupt to be
            //  generated by the receive side of serial port 0 indicating that data is
            //  available.  Once it is available, the data is DMA'ed into memory and
            //  the process continues.
            if(DMA3_CURR_X_COUNT > 1) {
                DMA3_CURR_ADDR += DMA3_X_MODIFY;
            }
        }
        if(DMA3_CURR_Y_COUNT > 1) {
            DMA3_CURR_ADDR += DMA3_Y_MODIFY;
            //Generate interrupt
        }
    }
    DMA3_CURR_ADDR += DMA3_X_MODIFY;
    //Generate interrupt
}

Personally, I found the following references to be much more useful than the partial version available from Google of the book you cited (but, I have a hardware background):

  1. ADSP-BF537 Blackfin Processor Hardware Reference 5-75 – 5-94
  2. ADSP-BF537 Data Sheet Rev. J

X_MODIFY is specified on page 5-88 of ADSP-BF537 Blackfin Processor Hardware Reference:

DMAx_X_MODIFY/MDMA_yy_X_MODIFY Registers

Makyen
  • 31,849
  • 12
  • 86
  • 121
0

In your code, X-MODIFY is the length of each data (in bytes) of iRxBuffer1.

Informs DMA, where (which address) to fetch the next data from. DMA bus address will be incremented by this X-MODIFY value.