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I know that systems with PowerPC assembler machine and others (like Tilera) adopt a weak store ordering, which does not guarantee that memory operations are visible to the system in program order (memory ordering problem). Thus, in these kinds of systems, explicit Memory Barrier instructions are required in synchronization situations... but how is it possible if these kinds of systems adopt store operations that have an asynchronous (no request-reply implementation) semantics?

Murray
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  • The loads and stores for a single thread of execution appear ordered to itself. When multithreading is introduced, the effects of weak consistency may be seen from other threads using the same data. – Dko Oct 19 '14 at 04:17

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Normally a store operation in the Tilera architecture does just "fire and forget" as you describe. But the memory fence instruction is provided for the case when you do need to know that the caches are coherent before proceeding. The MF instruction causes the CPU to wait until acknowledgements are received from all tiles that share the cache line that you've written. This involves request and response messages from the tile doing the write to the cache line's home tile, and from the home tile to any other tiles that share that cache line.

HAROLD RABBIE
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