Eight Bit Divider: Quotient and Remainder

Question

I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.

The errors I am receiving are:

Error-[ICPD] Invalid procedural driver combination
"divide.v", 2
Variable "Q" is driven by an invalid combination of procedural drivers. 
Variables written on left-hand of "always_comb" cannot be written to by any 
other processes, including other "always_comb" processes.
"divide.v", 2: logic [7:0] Q;
"divide.v", 8: always_comb  begin
if (x <= R) begin
...
"divide.v", 5: Q = 8'b0;

Error-[ICPD] Invalid procedural driver combination 
"divide.v", 2
Variable "R" is driven by an invalid combination of procedural drivers. 
Variables written on left-hand of "always_comb" cannot be written to by any 
other processes, including other "always_comb" processes.
"divide.v", 2: logic [7:0] R;
"divide.v", 8: always_comb  begin
if (x <= R) begin
...
"divide.v",6: R = y;

My SystemVerilog Code is:

module divider(input  logic [7:0] x,y,
               output logic [7:0] Q,R);
  initial
    begin
      Q = 8'd0;
      R = y;
    end
  always_comb
    begin
      if (x<=R)
        begin R <= R - x; Q <= Q + 8'd1; end
    end
endmodule

module test1; 

  logic [7:0] x,y,Q,R;

  divider Divider1 (x,y,Q,R);

  initial 
    begin
      x = 8'd2;
      y = 8'd8;
    end
endmodule

Using an `initial` block inside your divider module means it's not going to be synthesizable. Whenever you model sequential logic you need a reset scheme. — Tudor Timi, Sep 21 '14 at 07:55

score 3 · Accepted Answer · answered Sep 21 '14 at 04:59

Generally, in Verilog/SystemVerilog you cannot assign to a variable from two parallel blocks (with some exceptions). You are assigning to R and Q from two places: the initial block and the always_comb block.

Although the initial block only runs once, it runs in parallel with the always_comb block at the beginning of the simulation, which is a violation of this rule.

Why don't you get rid of the initial block and do everything in always_comb?

   always_comb
    begin
      Q = 8'd0;     // set initial value of Q
      R = y;        // set initial value of R
      ....          //THE REST OF THE ALGORITHM
    end

Also, you are missing using a loop!

score 1 · Answer 2 · edited May 23 '17 at 11:57

1

An important distinction between writing System Verilog (or any HDL) and writing in any software language (C/C++, Java, etc) is that System Verilog is designed to facilitate describing hardware structures while allowing for software-like testbenches, while software languages are designed to allow users to give instructions to an interpreter, VM or actual hardware. That being said, you need to think first about the hardware you are trying to describe and then write the associated HDL code. There are numerous posts describing the differences between HDLs and software languages (ex: Can Verilog/Systemverilog/VHDL be considered actor oriented programming languages?).

Looking at your code and flow chart you were given, it appears you are trying to use System Verilog as a programming language rather than a HDL. For example, initial blocks are generally only used in test benches and not in modules themselves. Also, as your algorithm is sequential, it is likely you will need a clock signal and registers, but the way your code lacks both.

Ideally, you should have a good idea of how to design digital hardware systems before trying to code any HDL, as this is the mentality you should have using HDLs. The goal is generally to translate a hardware design into HDL, so understanding digital design will help clarify alot.

edited May 23 '17 at 11:57

Community

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answered Sep 21 '14 at 00:46

Unn

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Although SystemVerilog is design to be an HDL, I don't see any reason not to use it for modeling simple software-like algorithms, specially when synthesis is not a concern. In fact the implementation of many algorithms in SV are very similar to that of C++ and similar languages and they are even synthesiszable. What does it really mean to say "using Verilog as a software language rather than HDL"? Some constructs of SystemVerilog are even more powerful than software languages. – Ari Sep 21 '14 at 05:09
The original post contained a link to a problem statement where the code had to be synthesized using Design Compiler. The above code is very very unsynthesizable, so I did not think it was worth explaining everything and addressing the larger issue instead. If synthesis is a concern, I think youd agree the given code needs a good deal of work to make it synthesizable. You can certainly implement software algorithms in SV, though typically the design is a bit different. The software constructs in SV are really designed as testbench tools, not to be used to run a program just by itself. – Unn Sep 21 '14 at 23:18
As for using SV as a software language, Im not sure why you'd ever want to do that. First, youd need a simulator to run the program (not to bad I suppose as may languages need a interpretor or VM). Second, while never benchmarked, something tells me the performance of such a program would be pretty bad. I dont disagree that alot of things are easier to do in SV than many software languages, but Im not sure that its worth it... – Unn Sep 21 '14 at 23:22

Eight Bit Divider: Quotient and Remainder

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