If in 8085, SP=0000H, which registers in which memory locations will be stored if PUSH B instruction is executed?
Will it be that register B content will be stored at FFFF and C at FFFE?
If in 8085, SP=0000H, which registers in which memory locations will be stored if PUSH B instruction is executed?
Will it be that register B content will be stored at FFFF and C at FFFE?
(Edited)
Ahhh, I see the question now.
This is not normally a situation that would arise in real-world code, of course. Code is generally loaded starting from low memory in this architecture, with data and stack above, so the program would be overwritten before you could provoke this situation.
There is no indication in the official Intel data sheets, or in any other documentation I've found, that an interrupt is triggered on stack pointer underflow.
So I would indeed expect that the instruction increments/decrements the SP register without any attempt to check for overflow, so memory addressing will indeed go from 0000 to FFFF. Since the behavior is unspecified, there's no reason for the manufacturer to waste gates testing for this case and handling it in any other way.
However, the official answer may be that this is Unspecified Behavior. To nail that down, you would have to find a statement from Intel, who originally designed this architecture. I've done a bit of searching (as noted above) but I simply don't see anything absolute.
Since I can't see any reason this would arise under normal circumstances, or any use for provoking it... I'm tempted to reduce all of the above to the Zen summation of "Mu."
So in order to answer this question, we need to really understand how the PUSH instruction actually works in 8085. Consider the following situation:
Register B has contents 0xAA
Register C has contents 0xBB
SP = 0x0000
Now, Let us assume the instruction encountered is PUSH. The PUSH instruction first decreases the stack pointer SP
B -> 0xAA
C -> 0xBB
SP -> 0xFFFF
and then stores the higher order register, decrements again and then stores the lower order registers as well.
B -> 0xAA
C -> 0xBB
0xFFFF -> 0xAA
0xFFFE -> 0xBB
SP -> 0xFFFE