How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

Question

Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function*......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation..

module state_delay;
reg Clk=1'b0;
reg [3:0]stmp=4'b0000;
integer i,a;


always
begin
#50 Clk=~Clk;
end

 always @(posedge Clk)
     begin
      a=1'b1;
      delay();
      a=1'b0;
      delay();
       a=1'b1;
      end 


  task delay();
   begin
   for(i=0;i==(stmp==4'b1111);i=i+1)
  begin
   @(posedge Clk)
    begin
    stmp=stmp+1;
    end
    end

  if(stmp==4'b1111)
  begin
  stmp=4'b0000;   
  end    

  end
  endtask


    endmodule

Actually friends I want this a=1'b0; delay(); a=1'b1; please help I already tried delay Generation Using Counter previously but it not works for me.....If you know same using Counter then please tell me......Thanks

Synthesisable Verilog is a hardware description language, what hardware are you wanting to imply? — Morgan, Jan 01 '14 at 14:30
Morgan Sir Actually I want to Interface an LCD 16*2(Contain Graphic Controller HD44780) or Nokia 6610 (Contain PCF8833 Graphic controller) sir but the main problem with both of them is this delay( devil for me).....sir for this I already written a code using **State Machine** but sir problem arises when I want delay whenever required in code....sir help me if you tell me I send you the whole code...please allow me so that I describe you in more detail...... — Shrikant Vaishnav, Jan 02 '14 at 07:42
Sir, for synthesisable digital design the only timing you have control of is clock edges. If you need a finer control of the timing you will have to use a faster clock. — Morgan, Jan 02 '14 at 12:14
You can find me on LinkedIn or Github if you follow the 'about me' link in [my profile](http://stackoverflow.com/users/97073/morgan). Then we can discuss. — Morgan, Jan 06 '14 at 08:28

score 0 · Answer 1 · answered Jan 01 '14 at 05:21

0

// will generate a delay of pow(2,WIDTH) clock cycles 
// between each change in the value of "a"
`define WIDTH 20

reg [`WIDTH:0] counter;
wire a = counter[`WIDTH];

always @(posedge Clk)
  counter <= counter + 1;

You have to choose a suitable value for WIDTH according to how much delay you want between changes in a and the rate of your Clk signal

answered Jan 01 '14 at 05:21

mcleod_ideafix

11,128
2
24
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This will not work with where the OP has tried to include delays. Where the delays have been added is not synthesisable. – Morgan Jan 01 '14 at 09:57
The OP explicity asked for this: "Actually friends I want this a=1'b0; delay(); a=1'b1; please help", so my answer is meant to cover that request. – mcleod_ideafix Jan 01 '14 at 14:54
The title of the question says 'Verilog Synthesis', Wrapping your code in a task I do not think will allow synthesis on `a=1'b0; delay(); a=1'b1;` – Morgan Jan 01 '14 at 20:01
Morgan sir I am confused sir Verilog Task is not Synthesizable? one more thing sir is Verilog function is synthesizable? – Shrikant Vaishnav Jan 02 '14 at 07:47
Sir @ShrikantVaishnav tasks are synthesizable as long as they do not contain timing information. Functions are syhthesizable but are never allowed to contain timing information. The theme here is **No Timing** allowed. – Morgan Jan 02 '14 at 11:54

score 0 · Answer 2 · edited May 23 '17 at 11:56

This question is a more succinct version of How to generate delay in verilog using Counter for Synthesis and call inside Always block?.

There is one section of code that I find troublesome:

always @(posedge Clk) begin
  a = 1'b1;
  delay() ;
  a = 1'b0;
end

NB: A good rule to stick to is to always use <= in edge triggered processes.

for now lets think of the delay(); task as #10ns; What we get with the current code would be:

time  0ns a = x;
time  1ns a = 1; //Posedge of clk
time  6ns a = 1; //Waiting on delay
time 11ns a = 0; //Delay completed

Using <= and I think you should see a similar behaviour. However when it comes to synthesis delays like #1ns can not be created and the whole thing will collapse back down to :

always @(posedge Clk) begin
  a <= 1'b0;
end

With a hardware description language a good approach is to consider what hardware we want to imply and describe it in the language. The construct always @(posedge Clk) is used to imply flip-flops, that is the output changes once per clock cycle. In the question we have a changing value 3 times, from 1 clock edge I do not know what hardware you are trying to imply.

You can not provide an inline synthesizable delay. For always @(posedge clk) blocks to be synthesizable they should be able to execute in zero time. You need to introduce a state machine to keep state between clock edges. I think I have already provided a good example on how to do this in my previous answer. If the delay is to be programmable then see mcleod_ideafix's answer.

Sir I am not getting you .......previously I am also confused when you said me -"you probably need to model high level state machine".....sir as I told you I had used all the tricks that I used in my embedded system for delay generation like task , for loop ,counter but none of these works for me...if possible can you tell me in more detail... — Shrikant Vaishnav, Jan 01 '14 at 18:20
@ShrikantVaishnav you need to think in hardware not software. What hardware are you trying to imply. `always@(posedge clk` is for a flip flop where the output changes once per clock cycle. — Morgan, Jan 01 '14 at 20:04

How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

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