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I am working on a project where i am trying to figure out how an interrupt is processed in the Global interrupt controller for a ARM architecture. I am working with pl390 interrupt controller. I see there is a line which is mentioned as legacy interrupts which bypasses the distributor logic. It is given that 2 interrupts can be programmed as a legacy interrupt. Can any one help with some explanation of what exactly is a legacy interrupt?. I trying searching online without any luck.

Nuetrino
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    See: [GIC interrupt bypass](http://stackoverflow.com/questions/19651470/what-is-the-use-case-of-gic-interrupt-bypass) – artless noise Nov 28 '13 at 18:25
  • @artlessnoise Thank you for the pointer. Unfortunately i do not have sufficient credits to suggest a synonym. – Nuetrino Nov 28 '13 at 20:40

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Legacy interrupts are the two interrupts that were in ARM before GIC arrived: nIRQ - normal interrupt request, and fIRQ - fast interrupt request.

Since legacy interrupts were made for single-core processors, and they don't support multi-core processors internally, the reason they bypass the distributor logic should be rather clear - the legacy interrupts are hardwired into one of the cores.

In short - it allows the CPU to work in backwards compatibility with older ARM specification. For example, a four-core ARM CPU will have 4 nIRQs and 4 fIRQs, separate for each of the cores. When you have an old piece of ARM-compatible hardware (which doesn't support GIC), you connect it to one of the core's nIRQ/fIRQ just as if you connected it to an old single-core CPU, and it will always execute on that one core.

More information can be found here - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CCHDBEBE.html

Luaan
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  • Thanks. it is quite clear. I hope i can implement this logic in my design so that i can get a picture of how many clock cycles are consumed by the distributor and cpu interface logic. Am i correct? – Nuetrino Nov 27 '13 at 10:18
  • That sounds possible, yes. I have to admit I kind of assumed that the distributor is cycle-synchronized with the cores themselves, so it'd always take the same time, but that's just an assumption, which may very well be wrong... However, on general principle, I'd not use legacy interrupts unless you're actually targetting legacy CPUs as well. I believe the legacy interrupts could be removed in the future (in some or all of future CPUs). – Luaan Nov 27 '13 at 10:20
  • Yes, That is my objective. It is clear from the documentation on many clock cycles it will take but i would want to verify it. So i think implementing legacy interrupts will give me that idea. thank you for the answer. – Nuetrino Nov 27 '13 at 10:33
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    It is also worth noting that nIRQ and nFIQ are still routed on through the GIC in most implementations - as private peripheral interrupts, routed only to the single core. The GIC does tend to run at a lower frequency than the CPU - I am not aware of any implementation that has the GIC running faster than 1/2 the core frequency - I think 1/3-1/4 are both common. Agreed that legacy interrupts should not be used for anything other than experiments. – unixsmurf Nov 27 '13 at 10:33
  • But is see the legacy interrupts ( which is understand is nIRQ and nFIQ) are just directly sent to the mux ( in the GIC) without being synchronized with the GIC clock ( glck) so i can assume that legacy interrupts are not affected by the gclk? Am i correct? – Nuetrino Nov 27 '13 at 10:42
  • You are, but I cannot find this specific behaviour in the specification, so it could be implementation specific - there could be CPUs that internally uses the GIC to send legacy interrupts (just as @unixsmurf said). Don't rely on unspecified behaviour if you're not ready to put massive amounts of work into testing on all the devices you want to support. – Luaan Nov 27 '13 at 11:09
  • @unixsmurf Well thank you for the comment. It is indeed treated as a PPI like you said but when in legacy mode it bypasses it. From ARM cortex documentation - PPI[0]"In legacy FIQ mode the legacy nFIQ pin, on a per Cortex-A9 processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-A9 processor. When a Cortex-A9 processor uses the Interrupt Controller, rather than the legacy pin in the legacy mode, by enabling its own Cortex-A9 processor interface, the legacy nFIQ pin is treated like other interrupt lines and uses ID28"- – Nuetrino Nov 29 '13 at 12:19
  • contd. So i cannot use the legacy interrupt since i have a interrupt controller or is there a way to bypass it? – Nuetrino Nov 29 '13 at 12:22
  • @Nuetrino The way I understand it, you can have the GIC in legacy mode too, you'll just lose the legacy pin-mapped interrupts through the GIC, they'll go directly instead. – Luaan Nov 29 '13 at 12:27
  • @Luaan I think i figured it out. The GIC can be set in legacy mode by setting some bits in the ICCICR register. I will try it out. thank you all for the comments. – Nuetrino Nov 29 '13 at 12:33