Synthesizable arithmetic shift in Verilog

Question

I recently came across this answer on stackoverflow.

With Verilog, once you take a part-select, the result is unsigned. Use the $signed system task on the part select to make it signed.

Is this method synthesizable (ie the system task $signed)

If it is not synthesizable, is there a different way to perform arithmetic shift on variables like a <= a>>>2 (this should give the quotient when a is divided by 4).

score 0 · Accepted Answer · answered Sep 08 '18 at 18:33

0

It certainly is synthesizable. Whether your particular tool supports it is another question.

You can also use a cast in SystemVerilog.

res = signed'(registers[0][0]) >>> 2;

answered Sep 08 '18 at 18:33

dave_59

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I will be using Vivado. Target is a Xilinx Zedboard – Parth K Sep 09 '18 at 10:27
Then it should support it – dave_59 Sep 10 '18 at 00:02

Synthesizable arithmetic shift in Verilog

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