Sandy Bridge
Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors (Core i7, i5, i3). The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Intel demonstrated an A1 stepping Sandy Bridge processor in 2009 during Intel Developer Forum (IDF), and released first products based on the architecture in January 2011 under the Core brand.
Top of a Core i5-2500 | |
| General information | |
|---|---|
| Launched | January 9, 2011 |
| Discontinued | September 27, 2013 |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer(s) |
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| Product code | 80619 (extreme desktop) 80620 (server LGA1356) 80621 (server LGA2011) 80623 (desktop) 80627 (mobile) |
| Performance | |
| Max. CPU clock rate | 1.60 GHz to 3.60 GHz |
| QPI speeds | 6.4 GT/s to 8.0 GT/s |
| DMI speeds | 4 GT/s |
| Cache | |
| L1 cache | 64 KB per core |
| L2 cache | 256 KB per core |
| L3 cache | 1 MB to 8 MB shared 10 MB to 15 MB (Extreme) 3 MB to 20 MB (Xeon) |
| Architecture and classification | |
| Microarchitecture | Sandy Bridge |
| Instruction set | x86-64 |
| Instructions | x86, x86-64 |
| Extensions | |
| Physical specifications | |
| Transistors |
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| Cores |
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| GPU(s) | HD Graphics 650 MHz to 1100 MHz HD Graphics 2000 650 MHz to 1250 MHz HD Graphics 3000 650 MHz to 1350 MHz HD Graphics P3000 850 MHz to 1350 MHz |
| Socket(s) | |
| Products, models, variants | |
| Product code name(s) |
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| Model(s) |
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| History | |
| Predecessor(s) | Nehalem (Tock) Westmere (Tick) |
| Successor(s) | Ivy Bridge (Tick) Haswell (Tock) |
| Support status | |
| Unsupported | |
Sandy Bridge is manufactured in the 32 nm process and has a soldered contact with the die and IHS (Integrated Heat Spreader), while Intel's subsequent generation Ivy Bridge uses a 22 nm die shrink and a TIM (Thermal Interface Material) between the die and the IHS.
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