Load–store architecture

In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).^: 9–12

Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.^: 9–12

For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.^: 9–12

The earliest example of a load–store architecture was the CDC 6600.^: 54–56 Almost all vector processors (including many GPUs) use the load–store approach.