2 nm process
In semiconductor manufacturing, the "2 nm process" is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the "3 nm" process node.
| Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
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Future
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The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.
| Process | Gate pitch | Metal pitch | Year |
|---|---|---|---|
| 7 nm | 60 nm | 40 nm | 2018 |
| 5 nm | 51 nm | 30 nm | 2020 |
| 3 nm | 48 nm | 24 nm | 2022 |
| 2 nm | 45 nm | 20 nm | 2024 |
| 1 nm | 42 nm | 16 nm | 2026 |
As such, "2 nm" is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous "3 nm" node generation.
As of May 2022, TSMC was expected to begun risk "2 nm" production at the end of 2024 and mass production in 2025; Intel at that time forecasted production in 2024, and Samsung in 2025.