Questions tagged [verification]

Verification checks whether a product complies with specifications and further fixed conditions.

Verification is a quality control process that evaluates whether the product under development complies with regulations, specifications, or conditions imposed at the start of a development phase, see http://en.wikipedia.org/wiki/Verification_and_Validation.

Verification spans from manual testing to formal methods, from early development to final product evaluation.

Although there is often not a clear divide, you should try to differentiate the following two notions:

  • Validation: "Are we trying to make the right thing?", i.e., is the product specified to the user's actual needs?
  • Verification: "Have we made what we were trying to make?", i.e., does the product conform to the specifications?

Also see:

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Verilog code error

I am getting error in this code. The code is for a 4 bit comparator. The error is that I get "unspecified" output in the out1 port. Please help. module bitCompare(num1,num2,out1,out2); parameter n = 3; output out1; output out2; …
Dib
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How will this loop work in SystemVerilog language?

How will this loop work in SystemVerilog language ? for(bit [2:0] i = 0; i < 4; i++) What will be the values of i after each iteration provided i is 3 bit wire ?
Ishan Kumar
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