How will this loop work in SystemVerilog language?

Question

How will this loop work in SystemVerilog language ?

for(bit [2:0] i = 0; i < 4; i++)

What will be the values of i after each iteration provided i is 3 bit wire ?

the values will be 0, 1, 2, 3, provided that the loop is in the right context. — Serge, May 09 '19 at 01:10

score 0 · Accepted Answer · edited May 09 '19 at 08:15

0

bit [2:0] i;

As i is 3-bit value, it can take values from 0-7.

so i will get values 0,1,2,3

edited May 09 '19 at 08:15

Matthew Taylor

answered May 09 '19 at 06:45

1

3 bit values can hold 0-7 – Jim Garrison May 09 '19 at 07:00
1

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