The register that points to the current location in the call-stack. Details vary by CPU architecture, but implicit use by push/pop instructions is common. (Please also include an architecture tag!)
CPU architectures that use a call-stack usually have an integer register dedicated to holding a pointer to the boundary between in-use and free stack space.
It's common to call this the "top" of the stack, even though it's the lowest/bottom address on most systems. (Having the stack grow downward while the heap grows upward is a very common convention (see also this Q&A). Diagrams of stack layouts get drawn either way—some with the high address at the top, and others with the low address at the top—so double-check that your terminology matches what you're reading or modifying.
NOTE: The term "stack pointer" only applies to a call-stack used as part of function call/return and/or saving of call-preserved registers for nested function calls, and making space (aka a stack frame) for local variables in a function.
It does not refer to to pointers into other stack data-structures used more generally.
The use of a stack pointer conveniently enables recursion and re-entrant functions (compared to static storage). See this MIPS Q&A.
Some architectures (e.g. x86) hard-wire the choice into the design by having interrupt-handlers use the stack-pointer register implicitly to push context onto the stack. x86 also has many instructions that implicitly use the stack pointer (like push / pop, call / ret), but those could be avoided if desired. However, there's no way around having a valid value in at least the kernel's [e/r]sp for interrupts.
Other architectures (notably mips) only use a specific register as the stack pointer by convention (i.e., the ABI/calling convention), and a different ABI could use a different register as the stack pointer with no loss of efficiency. Or even use no traditional stack at all, even for interrupt handling.
The stack pointer on various architectures:
x86:
sp/esp/rsp: one of the 8 (or 16 in 64-bit mode) integer registers usable as a source or destination of any instruction.(Because 16-bit
sp-relative addressing modes don't exist, 16-bit code is forced to copy the stack pointer to another register to access stack memory other than with push/pop. By convention, thebpregister is used to hold this copy.)- arm:
spis a synonym forr13. ARM switches register banks on interrupts instead of writing to memory through a stack pointer, but some ARM CPUs do implicitly use the stack pointer for interrupt context-saving in some situations. - arm64:
spis not a general-purpose register anymore, and there's no push-multiple, only one or a pair (and no mnemonic alias). - mips: Standard MIPS assembly language has aliases for most of the registers that correspond to their uses in the standard / recommended calling convention.
$spis an alias for$29. - powerpc:
r1is used as the stack pointer in the common PowerPC ABI - sparc:
%spis an alias for%o6, register number 14. It and%fp/%i6are involved in the sliding register-window stuff that SPARC does, instead of being global registers managed separately. See Understanding stacks and registers in the Sparc architecture(s). - itanium: Two stack pointers:
spfor automatic storage, and a second stack for spilling registers when the microarchitecture runs out of physical registers for the register-window mechanism. It looks somewhat similar to SPARC. - avr:
SP(composed of two 8-bit halves,SPHandSPL) is separate from the thirty-two 8-bit general-purpose registers. It can be used implicitly for push/pop, but only read/written directly as an I/O port. (Unlike three other 16-bit pointers composed of pairs of GP registers).
In general, questions should also be tagged with one of these architecture-specific tags!
