Questions tagged [pipelining]

In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one.

In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements.

Computer-related pipelines include:

  • Instruction pipelines, such as the classic RISC pipeline, which are used in central processing units (CPUs) to allow overlapping execution of multiple instructions with the same circuitry. The circuitry is usually divided up into stages, including instruction decoding, arithmetic, and register fetching stages, wherein each stage processes one instruction at a time.
  • Graphics pipelines, found in most graphics processing units (GPUs), which consist of multiple arithmetic units, or complete CPUs, that implement the various stages of common rendering operations (perspective projection, window clipping, color and light calculation, rendering, etc.).
  • Software pipelines, where commands can be written where the output of one operation is automatically fed to the next, following operation. The Unix system call pipe is a classic example of this concept, although other operating systems do support pipes as well.
  • HTTP pipelining, where multiple requests are sent without waiting for the result of the first request.

Source: Wikipedia

164 questions
1
vote
1 answer

Accessing variable outside redis pipelining function on Laravel

I am trying simple redis pipelining command using laravel and have an issue : $a = array("1","2","3"); Redis::pipeline(function($pipe) { for ($i = 0; $i < count($a); $i++) { $pipe->set("key:$a", $a); } }); And I got 'Undefined…
vugtis
  • 33
  • 5
1
vote
2 answers

What does it really mean to "Squash" an instruction?

Studying pipelined processors, and they make mention of predicting a branch being taken or not taken, inserting salient instructions in the sort of "interim" before we decide if the branch is taken or not, but then "squashing" them if we guess…
PinkElephantsOnParade
  • 6,452
  • 12
  • 53
  • 91
1
vote
2 answers

Parallelism in php

I want to optimize part of my code to improve performance.Since my application make use of commandline tool , i think it would certainly improve performance to execute lines of code in parallel rather than executing code sequentially
user2650277
  • 6,289
  • 17
  • 63
  • 132
1
vote
1 answer

Create a Data Hazard in a C Program

I am working on a problem where I am attempting to create different scenarios in different C programs such as Data Hazard Branch Evaluation Procedure Call This is in an attempt at learning pipelining and the different hazards that come up. So I am…
diaz994
  • 354
  • 3
  • 13
1
vote
1 answer

How to select a value of "measure-object" directly? (powershell)

I am wondering about something. Not very important, but I am curious now... Let's say we have a array: PS C:\> $array 3 1129 1063 1139 1299 4446 1135 1096 1216 1075 And now we want to have the average of the values above. So I use…
frupfrup
  • 187
  • 2
  • 12
1
vote
1 answer

Understanding stalls and branch delay slots

I am taking a course on Computer Architecture. I found this website from another University which has notes and videos which are helping me thus far: CS6810, Univ of Utah. I am working through some old homework assignments posted on that site, in…
basil
  • 690
  • 2
  • 11
  • 30
1
vote
1 answer

Pipelining -Mips instructions

I have confused by using pipelining in mips instruction. Any help will be great. Thanks in advance. What is the data dependency in the next two codes? Which of them can be solved by using stall (bubble) or forwarding. You can use the shape 1 for…
gek
  • 31
  • 6
1
vote
1 answer

Check headers before downloading with Net::HTTP::Pipeline

I am trying to parse a list of image URL's and get some basic information before I actually commit to download. Is the image there (solved with response.code?) Do I have the image already (want to look at type and size?) My script will check a…
Bretticus
  • 896
  • 6
  • 11
1
vote
0 answers

Http 1.1 pipelining support

I enabled http pipelining support in google chrome and observerd some problems in how data is received even when using big sites like amazon.com. What is the current support for pipelining from major servers ? I wonder if issues can be caused also…
Ghita
  • 4,465
  • 4
  • 42
  • 69
1
vote
0 answers

Fire requests outside the pipeline using netty.io

What is the correct way to implement using netty a proxy, but just in a stage in the pipeline For example ` @Override public void channelConnected(ChannelHandlerContext ctx, ChannelStateEvent e) { Channel ch = e.getChannel(); …
M. G.
  • 145
  • 1
  • 6
1
vote
0 answers

Is "Http pipelining" modified in iOS6?

"Http pipelining" in iOS5 can cause some issues, like switching images when rendering a web page in Safari. Some sites have reported this problem, like this one i.e. The origin of the problem is that pipelining "enables the browser to send several…
teleco
  • 21
  • 5
1
vote
3 answers

Is HTTP pipelining supported in iOS?

I'm wondering whether HTTP pipelining is supported in iOS or if I have to create the body of the multipart/mixed request myself.
znq
  • 44,613
  • 41
  • 116
  • 144
1
vote
1 answer

Quova TCP Keepalive? Pipelining?

One of my developers is reporting that the connection rate to our Quova servers has become a bottleneck. He reports that his attempt to set the TCP keepalive option in our Ruby code doesn't seem to be honored. I haven't yet looked at our code; but…
Jim Dennis
  • 17,054
  • 13
  • 68
  • 116
1
vote
1 answer

Are there any restrictions in writing multiple http responses?

I am building a HTTP proxy with netty, which supports HTTP pipelining. Therefore I receive multiple HttpRequest Objects on a single Channel and got the matching HttpResponse Objects. The order of the HttpResponse writes is the same than I got the…
Julian
  • 71
  • 6
0
votes
2 answers

What is the number of clock cycles required in the given sequence of Instruction using 5- stage pipelined CPU?

A 5 stage pipelined CPU has the following sequence of stages: IF – Instruction fetch from instrution memory. RD – Instruction decode and register read. EX – Execute: ALU operation for data and address computation. MA – Data memory access – for…
Prashant Bhardwaj
  • 1,203
  • 2
  • 18
  • 26