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Questions tagged [paging]

A memory-management technique where a computer stores and retrieves data from secondary storage for use in main memory. Memory is divided into equal sized pages so to not waste any memory.

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Not getting notified on PagedList updates

I am using the PagedList library in my app. It all works as expected, using the PagedListAdapter. However, I am not able to find how I can get a callback and be notified that the PagedList has been updated. At list's ItemKeyedDataSource is used to…
Sarquella
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Paging library data source with specific page index

Regarding the paging library in the arch. components It has three different datasources: PageKeyedDataSource: When a request requires next/previous index keys. ItemKeyedDataSource: When a request requires an item as a key. PositionalDataSource:…
mhdtouban
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UIScrollView: single tap scrolls it to top

I have the UIScrollView with pagingEnabled set to YES, and programmatically scroll its content to bottom: CGPoint contentOffset = scrollView.contentOffset; contentOffset.y = scrollView.contentSize.height - scrollView.frame.size.height; [scrollView…
indexless
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mysql union limit problem

I want a paging script working properly basically but the situation is a bit complex. I need to pick data from union of two sql queries. See the query below. I have a table book and a table bookvisit. What I want is here to show all books for…
Gajendra Bang
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Triple fault when jumping to 64-bit longmode

The following code that transitions from 32-bit protected mode (with A20 enabled) to 64-bit longmode seems to be giving me issues. I identity map the 1GiB page from 0x00000000 to 0x3fffffff; enable PAE; enable the longmode bit in the EFER MSR;…
Marcus Dem
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What is better datastructure to store user profiles in redis?

I want to store user's profiles in redis, as I have to frequently read multiple user's profiles.. there are two options I see at present: Option 1: - store separate hash key per user's profile [hash] - u1 profile {id: u1, name:user1,…
Suyog Kale
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What makes a TLB faster than a Page Table if they both require two memory accesses?

Just going off wikipedia: The page table, generally stored in main memory, keeps track of where the virtual pages are stored in the physical memory. This method uses two memory accesses (one for the page table entry, one for the byte) to access a…
m0meni
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Assembly Segmented Model 32bit Memory Limit

If a 32bit Operating System operated with a segmented memory model would their still be a 4GB limit? I was reading the Intel Pentium Processor Family Developer's Manual and it states that with a Segmented memory model that it is possible map up to…
user295190
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GridView don't Show on GridView_PageIndexChanging

I have a panel ViewStock where i am viewing stock in a gridview from database and DataBind() it via code. Allowed paging and created and event "OnPageIndexChanging" in gridview tag in html, Implemented the defined code above and paging in an event…
ARr0w
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jqGrid: Enable paging while converting HTML table to grid

Been googling all this while on how to convert an html table to something pagable and sortable, and I have stumbled across jqGrid jquery plugin. I've learned so far that we have to call tableToGrid() to convert the table (which we pass as a jquery…
deostroll
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Simultaneous existence of different-sized pages on Aarch64

According to the architecture overview document Aarch64 supports 4k and 64k pages. Some CPUs also support 16k pages. Looking into address translation scheme details I come to the conclusion that such CPUs don't support the simultaneous existence of…
ababo
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Disabling Paging in x86 32bit

I am trying to write directly to a physical memory location, so I am using an assembly function to first disable paging, write the value, and then re-enable paging, but for some reason a page fault is still triggered when trying to write the value.…
user12341234135245
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How many page tables do Intel x86-64 CPUs access to translate virtual memory?

I am trying to understand the number of tables looked-up, when translating a virtual address to a physical address. The Intel manual seems to state numerous…
user997112
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How does multilevel paging save memory?

I am confused with the concept of the multilevel paging scheme. Let a 32-bit virtual address and one page is of 4 KiB then I will have 220 pages/page table entries. Let one page table entry be of size 4 bytes, so the page table's size is 220 * 4…
Bishnu
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Is the data in a memory-mapped file guaranteed to flush sequentially?

I'm trying to implement a file storage mechanism which holds a number of variably-sized records in a single file with the guarantee that the set of records will always be recoverable into a consistent state, even if the system failed at a hardware…
Kennet Belenky
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