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I am confused with the concept of the multilevel paging scheme.

Let a 32-bit virtual address and one page is of 4 KiB then I will have 220 pages/page table entries.
Let one page table entry be of size 4 bytes, so the page table's size is 220 * 4 bytes.

If I divide the virtual address into 10 | 10 | 12, then what I understood is:

I have a page table directory, which is indexed by the most significant 10 bits of the virtual address, so it has 210 entries and points to 210 different page tables (that is, on the 2nd level).
Each 2nd level table again can be indexed by (the middle) 10 bits and the corresponding entry will hold the actual page frame number.

My questions are:

  • Is this correct at all?
  • Are the sizes of the page directory and the page table/s the same?
  • How does the multilevel paging scheme save memory?
cadaniluk
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Bishnu
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1 Answers1

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Yep, it's all correct. With only one level of page tables and 4 bytes per entry, the page table would have

4 GiB (maximal physical address space) / 4 KiB (size of one page frame) * 4 Bytes = 4 MiB

and accessing a physical address would be like

(page table entry)->(offset)


To lower the size of this big page table, a multilevel pagin scheme is employed, reducing the size to

2^10 Bytes * 4 + 2^10 Bytes * 4 = 8 KiB

and changing the resolution of a virtual address to a physical address to

(page directory entry)->(page table entry)->(offset)

This saves some bytes (4 MiB - 8 KiB) but has one drawback: one additional memory reference is required to convert a virtual to a physical address. Here, the TLB (Translation Lookaside Buffer) comes into play. It is a (compared to the L1 cache) small cache and stores the association of a virtual address to a physical address in hardware. Special hardware is used here, comparable to a hashtable (std::unordered_map in the C++ standard library), with the difference that it's implemented in hardware and therefore faster.


This is the default 32-bit Paging scheme employed in the x86 architecture. x86-64, PSE, PAE, somewhat change the mechanism with more levels of page tables, bigger page sizes (2 MiB, 4 MiB, and even 1 GiB), and a bigger physical address space (at most 64 GiB with PAE), leading to more levels of page tables. The x86-64's virtual addresses are 48 bits in size, leading to a huge address space per process (several TiB).

Note the difference between a page and a page frame. A page is the data, a page frame is the area in physical memory where pages are mapped at. There are systems where page's size = x * page frame's size, where x > 1.

cadaniluk
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  • thanks for quick response ! the 1st level page directory will have 2^10 entries which points to one-one 2nd level pages ,right ? i.e, 2^10 number of 2nd level pages !! So the total size should be (2^10 bytes * 4(page directry size) + 2^10(number of possible 2nd level tables) * 2^10 Bytes * 4(size of each 2nd level table)) ? Please correct. – Bishnu Oct 21 '15 at 12:36
  • @ashish Partially correct. The size of the page tables is composed of the size of the page directory + the size of the page table, yielding 8 KiBs on the default x86 setting. It is **not** multiplied by 2^10 Bytes again. – cadaniluk Oct 21 '15 at 12:38
  • I do agree to your point. But logically if you think number of 2nd level tables present in memory is equal to number of entry are there in page directory. Think I have 2 entries in page directory for 2 diff processes. Each entry points to 2 diff page table of some size. So size would be size of page directory + size of each page tables (i.e, 2). – Bishnu Oct 21 '15 at 12:43
  • @ashish If you have your favorite answer, please accept it in order to mark this problem as solved. – cadaniluk Oct 22 '15 at 15:01
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    @ashish I think your statement "Think I have 2 entries in page directory for 2 diff processes" is wrong. Different processes have their own page directory, after some study what I understood is multilevel paging saves memory because it does not allocate memory for every single page table, It allocates memory for a page table only when it is needed. Processes usually do not use the entire address space so allocating memory for mapping unused virtual address which is the case of single level paging is a overkill. Multilevel paging saves memory by mapping only used virtual addresses. – Farsan Rashid Jun 24 '17 at 03:50