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Questions tagged [nios]

Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGAs. Do not use this tag for Infblox NIOS appliances.

Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from DSP to system-control.

Nios II is comparable to MicroBlaze, a competing softcore CPU for the Xilinx family of FPGA. Unlike Microblaze, Nios II is licensable for standard-cell ASICs through a third-party IP provider, Synopsys Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.

Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios.

Do not use this tag for Infoblox NIOS appliances.

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Can't compile my system in Qsys

When trying to assemble the system according to the instructions in this document http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf I get this error message: Error: System.nios2_qsys_0: Reset slave sram_0.avalon_slave_0 not connected…
Niklas Rosencrantz
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Why do I need the mask instruction?

In Nios 2 with altera DE2 FPGA, I study the following code for interrupts At exception: check whether trap or interrupt exc_hand: rdctl et,estatus # read estatus andi et,et,1 # mask EPIE, bit 0 beq et,r0,noint # om EPIE == 0: no interrupt rdctl…
Niklas Rosencrantz
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I'm trying to write certain bits of a register hi to initiate power mode into sleep

My issue is I read the value of ADI_DEV_CORE_STATUS it remains as 0x2A, even after I write assert a 1 on bit 22 to enable power mode requests, and i print out the value directly after the value doesn't change. I'm trying send a a request to go to…
Cwells
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Please help me understand this nios2 code

We're supplied some assembly for nios2 that I don't fully understand. If we can start with this instruction then I don't understand what it's for: .set noat # required since we push r1 What does it mean? I looked in the manual but there…
Niklas Rosencrantz
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Bypassing the Data cache in a Nios II Processor

I have the following C source files which need to have some code removed and some code added to bypass the data cache on the Nios_2_r2c processor. I have no clue how to do this. File: switches.c #include "system.h" #include "pio_regs.h" #include…
Jason McKindly
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verilog parameter as input - nios II

I am looking out for a way so that I can send an input value from nios as a parameter to a verilog module. or Any other ways of assigning verilog parameter from input.
vlsi2013
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How to find system library properties in Nios 2 IDE v12?

I'm trying to make a project according to the spec but the dialogs seem to have changed completely in version 12. I don't nearly get similar dialogs in Nios 2 IDE v12. This is what I search: This is what I get, and nothing leads to a dialog like in…
Niklas Rosencrantz
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Why do I get compilation errors?

This is my program: #include #define uart0 0x860 #define uart1 0x880 void send_char( int output ) { int nothing; //while write on uart1 is not ready, wait while(!((*(uart1+8) & 0x0040) && 0x0040)) //+8 eller +2? 2 byte (8…
Niklas Rosencrantz
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Read Write Verilog Reg in NIOS

How can I read or write verilog reg (variable) in NIOS CPU? What should I do? I use DE0 NANO, cyclone IV and NIOS 2.
Prasetya Hutomo
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How to output the second digit here?

My output is supposed to look like this according to the spec: 00:00 00:01 00:12 01:23 12:34 23:45 34:56 45:67 56:78 67:89 78:9A 89:AB 9A:BC AB:CD BC:DE CD:EF DE:F0 EF:01 F0:12 01:23 12:34 and so on. I've written 2 assembly subroutines, one which…
Niklas Rosencrantz
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How to call this subroutine?

I'm learning MIPS 32 bit assembly in the NIOS II IDE and I've got a complete working subroutine that multiplies two numbers stored in r4 and r5 and return the result in r2: .global muladd # makes label "main" globally known …
Niklas Rosencrantz
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Writing this assembly program

I've a very precise specification for an assembly subroutine: Specification Name: The subroutine must be called hexasc. Input parameters: Only one, in register r4. The 4 least significant bits in register r4 specify a number, from 0 through 15.…
Niklas Rosencrantz
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Translating MIPS to machine code

.text .align 2 .global main .equ val,0x4712 # 16-bit binary code for 0x4712: 0100 0111 0001 0010 # Program code starts now main: movi r16,val movi…
Niklas Rosencrantz
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How to fix Error (10170): Verilog HDL syntax error at near text "("; expecting ";"

I am trying to instantiate a NiosII core in Quartus II and get the following compilation error message: Error (10170): Verilog HDL syntax error at myNiosII_inst.v(1) near text "("; expecting ";" I added myNiosII.qip and myNiosII_inst.v files to my…
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FPGA MOTOR CONTROL

I'm going to implement a motor control based on FPGA with a NIOS II soft processor, I need the system to meet the requirements of TUV and IEC 61508 certificates. I have read one solution to use a redundancy system, but I couldn't understand how I…
Abdullah Salah
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