Questions tagged [mmx]

MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel, introduced in 1997 with their P5-based Pentium line of microprocessors, designated as "Pentium with MMX Technology"

MMX is a trademark used to reference an extension to the Intel Architecture Instruction set. Officially Intel states the initials are meaningless. This extension adds 57 opcodes, a 64-bit quadword datatype and eight 64-bit registers. These registers can be addressed using the names mm0 through mm7.

To avoid compatibility problems with the context switch mechanisms in existing operating systems, these registers were aliases for the existing x87 FPU stack registers. Unlike the FP stack, the MMn registers are directly addressable.

The main usage of the MMX instruction set is based on the concept of packed data types, which means that instead of using the whole register for a single 64-bit integer, two 32-bit integers, four 16-bit integers, or eight 8-bit integers may be processed concurrently. Thus, the unofficial initials are known as "MultiMedia eXtension" or "Matrix Math eXtension."

The mapping of the MMX registers onto the existing FPU registers made it somewhat difficult to work with floating point and SIMD data in the same application.

MMX provides only integer operations

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In JWASM/MASM - pshufw produces Error A2030: Instruction or register not accepted in current CPU mode

I have the following assembly program that gives me an error when compilating: .686 .mmx .model flat,c .code MmxAdd proc push ebp mov ebp,esp mov eax, [ebp+24] cmp eax, AddOpTableCount jae BadAddOp …
Z3R0
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What are the names and meanings of the intrinsic vector element types, like epi64x or pi32?

The intel intrinsic functions have the subtype of the vector built into their names. For example, _mm_set1_ps is a ps, which is a packed single-precision aka. a float. Although the meaning of most of them is clear, their "full name" like packed…
Brotcrunsher
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What instruction set does SFENCE belong to?

I've been doing a good amount of research on AMD64 (x86-64) instructions, and its been kind of confusing. A lot of the time official CPU documentation doesn't designate instruction as part of a specific set, and the internet is sometimes split on…
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Add 32-bit words with saturation

Do you know any way to add with saturation 32-bit signed words using MMX/SSE assembler instructions? I can find 8/16 bits versions but no 32-bit ones.
LooPer
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Does Delphi support all MMX/SSE instructions?

I have this snippet of code: @combinerows: mov esi,eax and edi,Row1Mask and ebx,Row2Mask or ebx,edi //NewQ:= (Row1 and Row1Mask) or (Row2 and Row2Mask); //Result:= NewQ xor q; PUNPCKDQ mm4,mm5 <-- I get an error here …
Johan
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bad_alloc with unordered_map initializer_list and MMX instruction, possible heap corruption?

I am getting a bad_alloc thrown from the code below compiled with gcc (tried 4.9.3, 5.40 and 6.2). gdb tells me it happens on the last line with the initalizer_list for the unordered_map. If I comment out the mmx instruction _m_maskmovq there is no…
Eric Roller
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Why xmm logical shift is not working?

I loaded some content at xmm1 register, let's say it can be viewed as xmm1 = | bgra | bgra | bgra | bgra | (each one a dw) Now, i want to shift 1 byte logically to the right every double word so it ends up like this: xmm1 = | 0bgr | 0bgr | 0bgr |…
jscherman
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MMX Instructions and the x87 FPU Tag Word

section .data qVar1: dq 1 section .bss var28: resb 28 section .text _main: ; Use an MMX instruction movq mm0, [qVar1] ; Move quadword from r/m64 to mm. ; Read Tag Word fstenv [var28] …
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Porting MMX/SSE instructions to AltiVec

Let me preface this with.. I have extremely limited experience with ASM, and even less with SIMD. But it happens that I have the following MMX/SSE optimised code, that I would like to port across to AltiVec instructions for use on PPC/Cell…
Tim Kane
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Bus error when executing `emms` MMX instruction

I'm working on a port of some software with inline assembly because we took a few bug reports from a Debian maintainer under X32. The code is fine under both X86 and X64. We're catching a bus error on the emms instruction: ... 0x005520fd…
jww
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Benefit of using multiple SIMD instruction sets simultaneously

I'm writing a highly parallel application that's multithreaded. I've already got an SSE accelerated thread class written. If I were to write an MMX accelerated thread class, then run both at the same time (one SSE thread and one MMX thread per core)…
jakogut
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MMX v/s SSE2 Performance Comparison

Problem : I converted a MMX to code to corresponding SSE2 code. And I expected almost 1.5x-2x speedup. But both took exactly same time. Why is it? Scenario: I am learning SIMD instruction set and their performance comparison. I took an array…
Abid Rahman K
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How to use MMX in parallel with SSE operations

In Wikipedia, it says: The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations. Does it mean that processor can run…
Excalibur
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EMMS instruction execution time?

I'm reading The Art of Assembly: The MMX Instruction Set", After executing some MMX instructions, the EMMS instruction needs to be executed to reset the FPU. It states the EMMS instruction is quite slow. However when I profiled the EMMS execution…
John Scamps
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MMX sign extension

Does anyone know how to make sign extension from 16 bits words to 32 bits words using MMX registers? I would like to get two 32 bits sign extended words from two 16 bits words stored in a MMX register. No SSE4 instructions allowed. Regards
LooPer
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