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I've been doing a good amount of research on AMD64 (x86-64) instructions, and its been kind of confusing. A lot of the time official CPU documentation doesn't designate instruction as part of a specific set, and the internet is sometimes split on which instruction set a specific instruction belongs to. One example of this is SFENCE, with some sources claiming that it's part of EMMX and others claiming it's part of SSE.

I'm trying to organize all of them in a spreadsheet to help with learning, but these inconsistencies are incredibly frustrating in a field that is famously technical and precise.

Peter Cordes
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Badasahog
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    Why can't it be in both 3DNow! and SSE? Anyway, that was only relevant for x86, it is part of the base x86_64, so I don't know why you care. – Marc Glisse Mar 03 '22 at 16:40
  • what do you mean by base x86_64? what does that mean? – Badasahog Mar 03 '22 at 16:41
  • based on the wikichip page it should have these instruction sets: https://en.wikichip.org/wiki/amd/ryzen_5/1500x#Features – Badasahog Mar 03 '22 at 16:49
  • Every x86-64 CPU is guaranteed to support `sfence`. x86-64 guarantees SSE1 and SSE2, and SSE1 implies the presence of `sfence`. Similarly, x86-64 implies presence of P6 new instructions like `cmov` (and some x87 ones like `fcomi`, although usually we use SSE2 for scalar FP math on x86-64). That's what it means to say something is "baseline" for x86-64; it's not an extension to x86-64 that you have to check for separately, except in 32-bit code that might or might not be running on an x86-64 CPU. – Peter Cordes Mar 03 '22 at 21:44

1 Answers1

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EMMX is a subset of SSE, and sfence is part of both of them.

AMD did not immediately support all SSE instructions, but at first took a subset of it that did not require the new XMM registers (see near the bottom of the PDF), which became known as EMMX. That included for example pavgb mm0, mm1 (but not pavgb xmm0, xmm1), and also sfence.

All instructions that are in EMMX are also in SSE, processors that support SSE can execute EMMX code regardless of whether they "explicitly" support EMMX (which has a dedicated CPUID feature flag). The Zen 1 aka Summit Ridge you linked, supports EMMX implicitly: it does not have the corresponding feature flag set, but since it supports SSE, it also ends up supporting EMMX. Before Zen, AMD processors with SSE used to set the EMMX feature flag as well.

harold
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