The MESI protocol (known also as Illinois protocol) is a cache coherence and memory coherence protocol.
The MESI protocol (known also as Illinois protocol) is a cache coherence and memory coherence protocol. It or an extension like MESIF or MOESI is used nearly universally in multi-core CPUs and SMP systems.
http://en.wikipedia.org/wiki/MESI_protocol
MESI requires a core to take exclusive ownership of a cache line before writing to it, preventing multiple cores from storing conflicting values, or even from reading stale values.
(Cache itself is not the source of memory reordering: that's usually store buffers within individual cores. And on weakly-ordered ISAs, out-of-order execution of loads. See Does a memory barrier ensure that the cache coherence has been completed? no, cache is always coherent. A memory barrier waits for the store buffer to drain. It's a common misconception that stores make cache non-coherent and then barriers flush it manually.)
Relevant Q&As:
- Can num++ be atomic for 'int num'? explains how atomic RMW operations are typically implemented in modern x86, by holding a cache line in Modified state between the load and store, not responding to Invalidate or RFOs until after the atomic transaction.
