Stack Overflow
Stack Overflow

Questions tagged [makefile]

A makefile is an input file for the build control language/tool make. It specifies targets and dependencies along with associated commands to perform (a.k.a. recipes) to update the targets.

A makefile is usually an input file for the build control language/tool make. The make utility and the corresponding makefile format is standardized by POSIX.

Common newbie mistakes:

Makefile variable assignment error in echo - running two distinct commands in a recipe and not realizing the shell from the first will exit and lose any changes to the environment.

Make implementations

More information

25125 questions
96
votes
7 answers

Test whether a directory exists inside a makefile

In his answer @Grundlefleck explains how to check whether a directory exists or not. I tried some to use this inside a makefile as follow: foo.bak: foo.bar echo "foo" if [ -d "~/Dropbox" ]; then echo "Dir exists" fi Running make…
Dror
  • 12,174
  • 21
  • 90
  • 160
93
votes
5 answers

Can GNU make handle filenames with spaces?

I have a directory containing several files, some of which have spaces in their names: Test workspace/ Another directory/ file1.ext file2.ext demo 2012-03-23.odp I use GNU's $(wildcard) command on this directory, and then iterate over the result…
qntm
  • 4,147
  • 4
  • 27
  • 41
93
votes
2 answers

Escaping in makefile

I'm trying to do this in a makefile and it fails horribly: M_ARCH := $(shell g++ -dumpmachine | awk '{split($1,a,"-");print a[1]}') do you know why? I guess it has to do with escaping, but what and where?
Jonas Byström
  • 25,316
  • 23
  • 100
  • 147
93
votes
7 answers

What's a good directory structure for larger C++ projects using Makefile?

What's a good directory structure for larger C++ projects using Makefile ? This is how my directory structure looks at the moment: lib/ (class implementations *.cpp) include/ (class definitions *.h) tests/ (main.cpp for quick tests) Now, I'm not…
Olivier Lalonde
  • 19,423
  • 28
  • 76
  • 91
93
votes
1 answer

Makefile - missing separator

Possible Duplicate: Make error: missing separator Have this code in makefile: PROG = semsearch all: $(PROG) %: %.c gcc -o $@ $< -lpthread clean: rm $(PROG) and the error missing separator. stop. Can someone help me?
user1827257
  • 1,600
  • 4
  • 17
  • 24
92
votes
6 answers

How to use all *.c files in a directory with the Cmake build system?

I want to find all .c files under a directory and add them all to SRC files to compile in cmake. How can I do this in CMakeList.txt. for regular makefiles I can create SPECIFIED_SRC_FILE = $(foreach d,$(SPECIFIED_SRC_DIRS),$(wildcard $(addprefix…
user256537
91
votes
1 answer

:= vs = in make macros

Possible Duplicate: What is the difference between the GNU Makefile variable assignments =, ?=, := and +=? I only know very basic makefile syntax, and was reading through another project's makefile and came across := for macro declaration. Why…
Aaron Yodaiken
  • 19,163
  • 32
  • 103
  • 184
91
votes
16 answers

CMAKE_MAKE_PROGRAM not found

I have reached the end of my rope with CMake; it has so much potential, but I cannot seem to make it find the basic system tools (i.e. make) in order to function. SYMPTOMS CMake and the CMake GUI produce the following (after deleting the…
westie314
  • 929
  • 1
  • 6
  • 4
90
votes
4 answers

How to use LDFLAGS in makefile

I am new to Linux OS. I am trying to compile a .c file using a makefile. The math library has to be linked. My makefile looks like this: CC=gcc CFLAGS=-Wall -lm all:client .PHONY: clean clean: rm *~ *.o client When I run make, I get the…
user1802785
  • 1,013
  • 1
  • 8
  • 8
89
votes
9 answers

Run make in each subdirectory

I have a directory (root_dir), that contains a number of sub-directories (subdir1, subdir2, ...). I want to run the make in each directory in root_dir, using a Makefile placed in it. (Obviously supposed that each of subdir... has inside its own…
Alex
  • 9,891
  • 11
  • 53
  • 87
89
votes
5 answers

Exclude source file in compilation using Makefile

Is it possible to exclude a source file in the compilation process using wildcard function in a Makefile? Like have several source files, src/foo.cpp src/bar.cpp src/... Then in my makefile I have, SRC_FILES = $(wildcard src/*.cpp) But I want to…
domlao
  • 15,663
  • 34
  • 95
  • 134
88
votes
1 answer

Makefile:2: *** missing separator. Stop

I have two .cpp files namely decryptor.cpp and prod-ent.cpp. I have created a Makefile to for the compilation of both the files in Linux platform. all: decryptor.cpp prod-ent.cpp g++ prod-ent.cpp -o prod-ent -g g++ decryptor.cpp -o…
user3686363
  • 891
  • 1
  • 6
  • 4
87
votes
6 answers

Tool for debugging makefiles

I have a large legacy codebase with very complicated makefiles, with lots of variables. Sometimes I need to change them, and I find that it's very difficult to figure out why the change isn't working the way I expect. What I'd like to find is a…
mbyrne215
  • 2,304
  • 4
  • 21
  • 16
86
votes
5 answers

make : rule call rule

In a makefile, can I call a rule from another rule? Similar to: rule1: echo "bye" rule2: date rule3: @echo "hello" rule1
JuanPablo
  • 23,792
  • 39
  • 118
  • 164
86
votes
8 answers

Makefile to compile multiple C programs?

This is an incredibly simple question, but I'm new to makefiles. I am trying to make a makefile that will compile two independent programs: program1: gcc -o prog1 program1.c program2: gcc -o prog2 program2.c All the examples online go into…
Sarah
  • 861
  • 1
  • 7
  • 3
1 2 3
…
99 100