Questions tagged [makefile]

A makefile is an input file for the build control language/tool make. It specifies targets and dependencies along with associated commands to perform (a.k.a. recipes) to update the targets.

A makefile is usually an input file for the build control language/tool make. The make utility and the corresponding makefile format is standardized by POSIX.

Common newbie mistakes:

Makefile variable assignment error in echo - running two distinct commands in a recipe and not realizing the shell from the first will exit and lose any changes to the environment.

Make implementations

More information

25125 questions
106
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3 answers

Change working directory for npm scripts

Q: Is it possible to change the the context in which npm runs scripts? What I want to is the following: "scripts": { "test": "gulp mocha", "pre-install": "./deps/2.7/cpython/configure --prefix=$(pwd)/build --exec-prefix=$(pwd)/build && make -C…
eljefedelrodeodeljefe
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105
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9 answers

"multiple target patterns" Makefile error

My makefile fails with error: Makefile:34: *** multiple target patterns. Stop. What does it really mean, how can I fix this? (GNU make manual, written by Captain Obvious, isn't helping). Found it. I had rule in form: $(FOO): bar where FOO was…
Kornel
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105
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2 answers

How can I print message in Makefile?

I want to print some message while doing build process with a makefile. The following one can print the message, but it will not execute the script after it. How can I fix this issues? ifeq (yes, ${TEST}) CXXFLAGS := ${CXXFLAGS}…
Dan
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104
votes
15 answers

How to source a script in a Makefile?

Is there a better way to source a script, which sets env vars, from within a makefile? FLAG ?= 0 ifeq ($(FLAG),0) export FLAG=1 /bin/myshell -c ' ; $(MAKE) $@' else ...targets... endif
brooksbp
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104
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8 answers

Create a variable in a makefile by reading contents of another file

How can I create a variable on-the-fly from makefile, the value of which would be the entire contents of another data file.
Srinath
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104
votes
1 answer

How to change the extension of each file in a list with multiple extensions in GNU make?

In a GNU makefile, I am wondering if it is possible, with an file list input, to make a file list output with new extensions. In input, I get this list: FILES_IN=file1.doc file2.xls And I would like to build this variable in my makefile from…
TheFrancisOne
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103
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3 answers

How can I create a Makefile for C projects with SRC, OBJ, and BIN subdirectories?

A few months ago, I came up with the following generic Makefile for school assignments: # ------------------------------------------------ # Generic Makefile # # Author: yanick.rochon@gmail.com # Date : 2010-11-05 # # Changelog : # 0.01 - first…
Yanick Rochon
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103
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2 answers

Make error for ifeq: syntax error near unexpected token

I'm writing a Makefile that does string matching at one place, the code is like: if test ...; \ then \ shell scripts... \ fi ifeq ($(DIST_TYPE),nightly) shell scripts ... endif Here the first if is shell script, the second ifeq is GNU…
Ryan Li
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103
votes
10 answers

tar: file changed as we read it

I am using make and tar to backup. When executing makefile, tar command shows file changed as we read it. In this case, the tar package is ok when the warning comes up but it stops the tar command for the following backup the file showing the…
warem
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102
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12 answers

Promising alternatives to make?

I've been using make and makefiles for many many years, and although the concept is sound, the implementation has something to be desired. Has anyone found any good alternatives to make that don't overcomplicate the problem?
mike511
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101
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7 answers

How to use GNU Make on Windows?

I installed MinGW and MSYS, added C:\MinGW\bin to PATH but I still can't run Makefile on Windows' cmd. I would like to run cmd.exe and there type, for example, make all but my cmd says that there is no such command. What should I do? I don't want…
yak
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100
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16 answers

List goals/targets in GNU make that contain variables in their definition

I have a fairly large makefile that creates a number of targets on the fly by computing names from variables. (eg foo$(VAR) : $(PREREQS)). Is there any way that gnu make can be convinced to spit out a list of targets after it has expanded these…
BitShifter
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99
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9 answers

How can I have a Makefile automatically rebuild source files that include a modified header file? (In C/C++)

I have the following makefile that I use to build a program (a kernel, actually) that I'm working on. Its from scratch and I'm learning about the process, so its not perfect, but I think its powerful enough at this point for my level of experience…
Blank
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98
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6 answers

What does "make oldconfig" do exactly in the Linux kernel makefile?

Can anyone explain what the target "oldconfig" does exactly in the Linux kernel makefile? I see it referenced in some build documentation but never explained what it does exactly.
fred basset
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97
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3 answers

Remove item from a Makefile variable?

I have a makefile, which includes several other makefiles, which in turn all add to a variable like this: VAR := Something SomethingElse VAR += SomeOtherThing (...) Now I wish to remove SomethingElse from the VAR variable. What do I put in place…
Bjarke Freund-Hansen
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