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Questions tagged [intel]

For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture.

Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California, United States. Intel is the inventor of the x86 processor architecture and makes central processing units, motherboard chipsets, graphic processing units, network interface controllers and much more devices related to communications and computing.

In addition to their hardware offerings Intel also produces a variety of software including compilers, libraries for mathematical computation(Intel MKL), threading(OpenMP, Intel Performance Primatives, Threading Building Blocks), parallel communication(MPI,OFED/True Scale Infiniband Stack) and several other products included in the Intel Parallel Studio toolkit. In addition to these offerings which are widely used in HPC Intel also produces software for datacenter management and is one of the most prolific contributors to the Linux kernel.

This tag should be used for questions about Intel hardware and software.

The x86 and/or x86-64 tags are better choices for questions about assembly programming for the architecture, rather than things like performance tuning specifically for Intel's implementation of x86.

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Confusing results on CHA aware Jacobi 2D microbenchmark

I aim to implement a lower latency version of jacobi 2d stencil. The default version is depicted below in the code snippet: for(auto i = 1; i < N - 1; ++i) { for(auto j = 1; j < N - 1; ++j) { *B[i][j] = 0.2 * (*A[i][j] + *A[i][j-1] +…
avernus
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Measure dirty evicts of Caches using Linux Perf or other Perf monitors

Linux perf tool provides data on cache behavior for some events like "LLC-load-misses" that counts reads that missed LLC and "LLC-store-misses" counts write misses. Now, what exactly is a write miss here? Typically, since a write miss would create…
ShAd
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Support of Intel's MLE / DRTM in long mode

I am currently working on an x86 operating system that is booted the way similar to tboot. A lot of the logic is copied from tboot. Currently the OS' boot sequence is: BIOS launches the OS using multiboot standard, OS runs in protected mode…
Eric Stdlib
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HAXM not installing.. The system requirements are not satisfied

While installing Android Studio, I got the error that HAXM didn't install.. so i tried installing haxm using the solutions provided in stackoverflow, youtube etc.. but its not working. I have enabled virtualization(screenshot) etc.. still this…
Aniket Kumar Paul
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Does the Intel 64 and IA-32 Architectures Software Developer's Manual Description of OUT Instruction contain errors?

In Volume 2, CHAPTER 4 INSTRUCTION SET REFERENCE, M-U, the description of OUT Instruction has this sentence: "using the DX register as a source operand allows I/O ports from 0 to 65,535 to be accessed." I think when using OUT instruction, the DX…
dongli si
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Invalidation of the cache from L1 cache

Suppose that a cache line with variable X is simultaneously uploaded to L1d of CPU0 and L1d of CPU1. After changing the value of X from CPU0, when CPU1's L1d cache line is invalidated, Is it impossible for CPU1 to copy the variable X from CPU0's L1d…
whitebear
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How can install intel OpenCL integrations with visual studio?

I have tried and installed every possible combination of Intel SDK toolkits and Visual Studio (2017/19/21) in the hope that the OpenCL integrations (project templates, compiler, and header and libraries) would be added as described…
Patrick Kwok
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There are errors when using Intel DPC++ compiler to compile subroutine with Eigen head file

Just got stuck in compiling a simple C++ program with Eigen C++ when using intel oneAPI DPC++/C++ compiler: The example contains two .cpp files (main.cpp and Preprocessing.cpp) and one include file (struct_INFO.h). I don't know why the compiler…
Jason
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Build or run Mac Catalyst apps on Intel Mac?

I have successfully built an app using Mac Catalyst. It runs on iPhone, iPad, and M1 Macs, and is available now in the App Store as "Designed for iPad". So far, so good. But it's not available for Intel-based Macs, and I haven't been able to build a…
Rick Holzgrafe
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Access to virtualization exception area inside a guest OS

I am currently implementing a solution that utilizes the Virtualization exception #VE in Intel CPUs. My code enables #VE in KVM so the guest OS can handle it. According to Intel SDM though, the information about the #VE is stored in the…
silentnights
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accessing pci configuration space in real mode

I'm trying to write assembly to access pci configuration space. what I'm trying to do is basically what this article does. https://sites.google.com/site/pinczakko/pinczakko-s-guide-to-award-bios-reverse-engineering my question is, because I'm…
M K
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INTEL X86，why do align access and non-align access have same performance?

From INTEL CPU manual(Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D):System Programming Guide 8.1.1), it says "nonaligned data accesses will seriously impact the performance of the processor". Then I do a…
Hankin
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Effective total time for a callee function is higher than that of caller function in intel-vtune

I have a multi-threading application and when I run vtune-profiler on it, under the caller/callee tab, I see that the callee function's CPU Time: Total - Effective Time is larger than caller function's CPU Time: Total - Effective Time. eg. caller…
yashC
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Access behavior of MM_PREFETCH intrinsic - Intel

The documentation available here mentions that data available at the specified address is brought from memory to the cache line (the cache level provided as a hint). However, I am confused whether or not the LLC is also accessed (assuming the hint…
Harsh Kumar
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Measuring Stack Space

Recently I interviewed with Intel, and I was asked this question How would you measure the stack space without using the task manager, when an application is running on a computer? Write an algorithm if possible I have no idea how to approach the…
Turing101
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