Questions tagged [intel]

For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture.

Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California, United States. Intel is the inventor of the x86 processor architecture and makes central processing units, motherboard chipsets, graphic processing units, network interface controllers and much more devices related to communications and computing.

In addition to their hardware offerings Intel also produces a variety of software including compilers, libraries for mathematical computation(Intel MKL), threading(OpenMP, Intel Performance Primatives, Threading Building Blocks), parallel communication(MPI,OFED/True Scale Infiniband Stack) and several other products included in the Intel Parallel Studio toolkit. In addition to these offerings which are widely used in HPC Intel also produces software for datacenter management and is one of the most prolific contributors to the Linux kernel.

This tag should be used for questions about Intel hardware and software.

The x86 and/or x86-64 tags are better choices for questions about assembly programming for the architecture, rather than things like performance tuning specifically for Intel's implementation of x86.


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Debian Firmware bug TSC_DEADLINE disabled due to Errata

On Debian, when machine is boots, it shows error: [Firmware Bug]: TSC_DEADLINE disabled due to Errata; please update microcode to version: 0xb2 (or later) I did sudo apt-get update && sudo apt-get upgrade && sudo apt-get dist-upgrade and it…
Yehuda
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Intel Intrinsics guide - Latency and Throughput

Can somebody explain the Latency and the Throughput values given in the Intel Intrinsic Guide? Have I understood it correctly that the latency is the amount of time units an instruction takes to run, and the throughput is the number of instructions…
Philipp Neufeld
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How can I write self-modifying code that runs efficiently on modern x64 processors?

I'm trying to speed up a variable-bitwidth integer compression scheme and I'm interested in generating and executing assembly code on-the-fly. Currently a lot of time is spent on mispredicted indirect branches, and generating code based on the…
Nathan Kurz
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whats the purpose of x86 cr0 WP bit?

in x86 CPU, there is control register number 0. the 16'th bit of this register indicates "Write Protection" setting. if this bit is cleared, CPU is able to overwrite Read Only data. (configured in page table entry) in memory. if this bit is set, CPU…
daehee
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Using __m256d registers

How do you use __m256d? Say I want to use the Intel AVX instruction _mm256_add_pd on a simple Vector3 class with 3-64 bit double precision components (x, y, and z). What is the correct way to use this? Since x, y and z are members of the Vector3…
bobobobo
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How is concurrency done in Intel x86 assembly?

I'm curious to know how one would code concurrent software on Intel x86 assembly. Both threads or coroutines with yielding are interesting. I realize this isn't practical to do in assembly, but I'm just curious.
Tower
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How to enable VMX in the HAXM installation?

This is frustrating af. My problem seems not to be unique as you can see, there are a lot of similar issues opened here in SO but after playing trial and error for i-dont-know-how-many-hours i give up. Some quick context: Installed Android Studio.…
daenius
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Why both? vperm2f128 (avx) vs vperm2i128 (avx2)

avx introduced the instruction vperm2f128 (exposed via _mm256_permute2f128_si256), while avx2 introduced vperm2i128 (exposed via _mm256_permute2x128_si256). They both seem to be doing exactly the same, and their respective latencies and throughputs…
mSSM
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Uninstalling intel HAXM on Mac (El Capitan)

I ran into an error after installing VMware Fusion on my mac, that it couldn't find /dev/vmmon. After some digging, I've learned that there are only so many available character devices, and that other software I have has consumed them. Since I…
Tim Potter
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Interrupt routing for PCIe slot directly connected to the CPUs

If we look at a Haswell architectural diagram today we can see that there are PCIe lanes directly connected to the CPU (for graphics) as well as some of them routed to the the platform controller hub (southbridge replacement): If we look Intel 8…
zgerd
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Difference between the AVX instructions vxorpd and vpxor

According to the Intel Intrinsics Guide, vxorpd ymm, ymm, ymm: Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in a and b, and store the results in dst. vpxor ymm, ymm, ymm: Compute the bitwise XOR of 256 bits…
netvope
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What is the overhead of using Intel Last Branch Record?

Last Branch Record refers to a collection of register pairs (MSRs) that store the source and destination addresses related to recently executed branches. http://css.csail.mit.edu/6.858/2012/readings/ia32/ia32-3b.pdf document has more information in…
user655617
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Is an __m128i variable zero?

How do I test if a __m128i variable has any nonzero value on SSE-2-and-earlier processors?
user541686
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Intel TBB will work on AMD processors?

Possible Duplicate: AMD multi-core programming Is Intel TBB processor dependent? Will it work on amd or on ARM (under meeGo for example?)
Rella
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Is the Intel C++ Compiler (19.0) now only using the Clang front-end (i.e. already abandoned EDG)?

In 16.0, the Intel C++ Compiler provided two compilers (one based on EDG, another based on Clang). From the 16.0 documentation: Using the Command Line To invoke the compiler from the command line, use a command similar to the following: For C…
Zeson
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