Questions tagged [gtkwave]

GTKWave is an open-source wave visualization software which is compatible with many known wave formats, including wif (created by modelsim). It is commonly used to visualize the testbench output of VHDL/Verilog implementations.

More information is available at the GTKWave site.

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How to specify annotations in VCD files?

In a VCD file I would like to specify that some events occurred at a particular time. To that end, I tried to define a single bit signal which value is almost the time 0, and switching this value to 0 and then back to 1 in the same time (at the time…
Manuel Selva
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How to display values of "parameters" and "localparaters" in gtkwave iverilog simulation?

Gtkwave is displaying all the registers and signal values in the simulation using iverilog, but I can not find a way to display the parameters and localparameter values. Any advice?
AZ123
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Unable to output data entered into a register

I have a simple program. I am trying to input the counter output into a memory address register and output the data that is in the memory address register. Memory Address Register Code: library ieee; use ieee.std_logic_1164.all; entity mar…
Mahmoud Abdel-Rahman
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Unable to get Rocket Chip waveforms for GTKwaves

I want to run a program on Rocket core and observe all the signals in corresponding registers in GTKwave (e.g. PC, register file, ALU registers and wires etc.) However, the only I get (both in chipyard and rocket chip) is some strange list of wires…
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Why isn't ModelSIM displaying timing waveforms, whereas GTKWave does?

I am kinda new to verilog and struggling with all the basic concepts. I am trying to display the timing waveform in ModelSim, where is simply throws "# (vish-4014) No objects found matching '/tb/*'. "(in my case). Whereas when I simulate the…
afaq
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How to test bench VHDL signals and show them In GTKWAVE?

I emulated this VHDL code using GHDL in terminal, no errors occured, but when I imported .vcd file into GTKWAVE no signal shown up. SCREENSHOT OF GTKWAVE Desing Code: Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; entity EXO…
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Incorrect debugging information when troubleshooting vcd2fst segmentation fault

I am using the vcd2fst tool (installed with GTKwave) to convert a .vcd file to .fst using the following command: vcd2fst -v wave.vcd -f dummy.fst This works fine in my host Ubuntu 18.04 machine. Meanwhile, when the same command (and the same…
noureddine-as
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Displaying verilog structures in gtkwave from FSDB

GTKwave 3.3 does not display Verilog structures dumped by VCS into FSDB. I declare a typedef: typedef struct packed { logic [DATA_WIDTH-1:0] data; logic valid; logic fp; } in_tdef; And then use it as…
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Shift right in vhdl without using srl

I am currently working on implementing a code that performs a right shift on a 23-bit array. However, I am facing some issues: I'm not sure why, but when I visualize the 'din' signal using GTKWAVE, I always find a '0' at the beginning of my input…
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Input assignment in testbench and output values (ghdl and gtkwave)

I'm going straight to specifics. I'm using Ubuntu 14.04LTS, GHDL compiler and GTKWave for simulation. I have two files for simulating a simple 2-multiplexer: mux2.vhd and mux2_testbench.vhd This is the code for mux2.vhd -- Libraries library…
RbeJG
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why clk_o2 is x here?

I've tried to delay in the initial but it doesn't work I'm a newbie in Verilog and it was a training problem The ClockDivisor Code The Test bensh The Result I get x at clk_o2 if I change it on the negative edge
Adham Nour
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How to display Value Change Dump(VCD) files on webpages ? I want to visualize a VCD file on my webpage

in my case a vcd file is generated on server and i want to visualize that file in gtkwave software on webpage so that client can see the file in gtkwave. I am not an expert web developer please help if anyone knows how to do it. thanks in advance…
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