ALDEC Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
ALDEC Active-HDL provides
- Project Management
- Graphical/Text Design Entry
- Simulation and Debugging
- Documentation in HTML/PDF
for FPGA design using mixed HDL languages with a common kernel mixed-language simulator (VHDL, Verilog, SystemVerilog (Design), SystemC).
This tag is intended for questions pertaining to Active-HDL unique features.
