How to make synchronous counter that counts 3,5,7,0 and repeats?

Question

I'm assuming I'll need three T-flip-flops?

Construct the truth table with the 3 input bits and the 3 next state output bits. Then construct the Karnaugh maps for the 3 next state output bits. From those, determine the minimized Product Of Sums or Sum of Products, and from that design the gate & flip-flop circuit. — Andrew, Feb 23 '22 at 23:47

score -1 · Answer 1 · answered Mar 24 '12 at 14:20

-1

Hmm, you could get it simpler if treat in another way: two upper bits are circling 0,1,2,3, and lower one is OR of upper ones.

Something like (pseudocode)

wire V[1:0];
wire Out[2:0];
@(posedge clk) {
  V += 1;
  Out[2] <= V[1]; Out[1] <= V[0]; Out[0] <= V[1] | V[0];
}

answered Mar 24 '12 at 14:20

Netch

Initial state is wrong. OP is asking for the digital design. – Andrew Feb 23 '22 at 23:02

1 Answers1