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I have simulated 4 different binaries in the SimpleScalar simulation tool and for every binary the L2 unified miss rate is greater than L1 data miss rate.

In my assignment I am suppose to do some analysis. First thing that come to my mind is L2 miss rate should be smaller since it has higher level in hierarchy and more size than L1 cache.

Besides, as far as I know, L2 is referenced only when there is a miss in L1 cache. From my point of view, L2 should have the data that L1 does not have most of the time so its miss rate should be less.

However, results are not close to what I expected.

For instance,

  • L1 Data Miss Rate : 0.0269
  • L2 Unified Miss Rate : 0.0566

The miss rate is determined as misses / references to cache.

What is wrong with my approach? Why L2 miss rate is greater than L1?

Cody Gray - on strike
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emre nevayeshirazi
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  • how big are the problems (code + data) relative to the caches? are they all larger, all smaller, or cover a range? what are typical reference counts for the two caches (ie what are the absolute numbers above, instead of the ratios)? – andrew cooke Mar 18 '12 at 01:44
  • for example, if the problem is size n and everything fits in L1 then you will have n misses in L1 and L2, but kn references in L1 and n references in L2. so L1 ratio will be small and L2 ratio unity. absolute numbers and size are critical. – andrew cooke Mar 18 '12 at 01:59
  • my input file looks like this : '25000 e 2231'. I have no idea what it means. Thanks for help. – emre nevayeshirazi Mar 18 '12 at 02:31

1 Answers1

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Hit/miss rates only consider data accesses that tried to use the particular cache. So if the data you are using is already in a register, there is no need to even check the L1 cache, so L1 does not register either a hit nor a miss. Similarly, if the data is found in L1, L2 does not register either a hit nor a miss. The miss rate for L2 is basically (# times data was not in L2) divide by (# of times L2 was accessed), or equivalently (# times data was not in L2) divide by (# of times data was not in L1).

Nicu Stiurca
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