How to combine multiple arrays into one array in Verilog?

Question

Here is my code:

module MIPS_Processor();
    reg [7:0] mem [0:4095];      // 4K memory cells that are 8 bits wide
    reg [7:0] code[0:1023];      // 1K memory cells that are 8 bits wide
    reg [31:0] registers[0:31];  // 32 registers that are 32 bits wide
    reg [31:0] PC;               // The program counter

    initial
        begin
            PC = 0;
        end

    always
        begin
            // 1. Fetch an instruction from memory
            bit [31:0] instruction = {{code[PC * 8 + 7:PC * 8 + 0]},
                                     {code[(PC + 1) * 8 + 7:(PC + 1) * 8 + 0]},
                                     {code[(PC + 2) * 8 + 7:(PC + 2) * 8 + 0]},
                                     {code[(PC + 3) * 8 + 7:(PC + 3) * 8 + 0]}};

            // 2. Increment the program counter register (by the instruction length)
            PC = PC + 4;

            // Rest of the code

    end
endmodule

How can I combine the 4 arrays into one array to fetch the instruction from the code? The code above does not compile!

EDIT:

After changing the code to what @toolic suggested:

bit [31:0] instruction = {
                     code[PC + 0],
                     code[PC + 1],
                     code[PC + 2],
                     code[PC + 3]
};

still, it does not compile:

Using Xilinx:

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "MIPS_Processor.v" in library work
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 expecting ']', found ':'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '='
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 39 unexpected token: '{'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 40 expecting '.', found ','
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 41 expecting '.', found ','
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 42 expecting '.', found ','
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 44 expecting '.', found '}'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: '='
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 unexpected token: 'PC'
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'end', found '+'
Module <MIPS_Processor> compiled
ERROR:HDLCompilers:26 - "MIPS_Processor.v" line 46 expecting 'endmodule', found '4'
Analysis of file <"MIPS_Processor.prj"> failed.
--> 

Total memory usage is 274336 kilobytes

Number of errors   :   11 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)


Process "Synthesize - XST" failed

Using Verilogger Extreme:

enter image description here

As an aside, MIPS uses word addressed memory with byte enables, so changing your code so that it models your Verilog memory as an array of words would better match the hardware, and would make detecting miss-aligned memory accesses easier in the rest of your Verilog code. — markgz, Mar 16 '12 at 23:51

toolic · Accepted Answer · 2012-03-16T23:50:30.177

3

To form an instruction word from 4 consecutive bytes of the code memory:

// 1. Fetch an instruction from memory
bit [31:0] instruction = {
                         code[PC + 0],
                         code[PC + 1],
                         code[PC + 2],
                         code[PC + 3]
};

edited Mar 16 '12 at 23:50

answered Mar 16 '12 at 23:43

toolic

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How to combine multiple arrays into one array in Verilog?

1 Answers1