I've read almost all questions about CUDA, C++ & makefiles here, but still can't figure solution to my problem.
I have a some .cpp
files & some .cu
files inside src/
directory of my project (along with .h
& .cuh
), and I'd like to build my application with a makefile.
I have tried to do it this way:
SRC_DIR = src
OBJ_DIR = obj
CPP_FILES = $(wildcard $(SRC_DIR)/*.cpp)
CU_FILES = $(wildcard $(SRC_DIR)/*.cu)
H_FILES = $(wildcard $(SRC_DIR)/*.h)
CUH_FILES = $(wildcard $(SRC_DIR)/*.cuh)
OBJ_FILES = $(addprefix $(OBJ_DIR)/,$(notdir $(CPP_FILES:.cpp=.o)))
CUO_FILES = $(addprefix $(OBJ_DIR)/,$(notdir $(CU_FILES:.cu=.cu.o)))
$(TARGET) : $(OBJ_FILES) $(CUO_FILES)
$(LD) $(LDFLAGS) $(LIB_CUDA) -o $@ $?
$(CUO_FILES) : $(CU_FILES) $(CUH_FILES)
$(NVCC) $(NVCCFLAGS) $(INCLUDES) -c -o $@ $<
$(OBJ_DIR)/%.o : $(SRC_DIR)/%.cpp $(H_FILES)
$(NVCC) $(NVCCFLAGS) $(INCLUDES) -c -o $@ $<
And it was OK until I've got a second .cu file. And then I tried:
<... previous part stays the same ...>
OBJS = $(patsubst %.cpp,$(OBJ_DIR)/%.o,$(notdir $(CPP_FILES)))
OBJS += $(patsubst %.cu,$(OBJ_DIR)/%.cu.o,$(notdir $(CU_FILES)))
$(TARGET) : $(OBJS)
$(LD) $(LDFLAGS) $(LIB_CUDA) -o $@ $?
$(OBJ_DIR)/%.cu.o : $(SRC_DIR)/%.cu $(CUH_FILES)
$(NVCC) $(NVCCFLAGS) $(INCLUDES) -c -o $@ $<
$(OBJ_DIR)/%.o : $(SRC_DIR)/%.cpp $(H_FILES)
$(NVCC) $(NVCCFLAGS) $(INCLUDES) -c -o $@ $<
But make can't figure out how to make any of the .cu.o
files now.
How should I modify this thing to build my application?
Thanks in advance!
Upd - output of make with second makefile:
/usr/local/cuda/bin/nvcc -I/usr/local/cuda/include -c -o obj/main.o src/main.cpp
/usr/local/cuda/bin/nvcc -I/usr/local/cuda/include -c -o obj/util.o src/util.cpp
make: *** No rule to make target `obj/thrust.cu.o', needed by `DCG'. Stop.
project files (src/):
- main.cpp
- utils.h
- util.cpp
- thrust.cu
- thrust.cuh
- cuda-utils.cu
- cuda-utils.cuh