VHDL ALU undefined value

Question

I'm learning VHDL for programming a FPGA, basic (but hard-for-me) projects. I have this ALU. It is supossed to be a 4-bit ALU. But when I want to make the Add operation the value of result is UUUU. For all other operations is working fine.

Any advise?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


entity ALU is
    Port (
                clk: in std_logic;
                reset: in std_logic;
                operation: in std_logic_vector (2 downto 0)
          );
end ALU;

architecture Behavioral of ALU is
    signal A : std_logic_vector (3 downto 0) := "0001";
    signal B : std_logic_vector (3 downto 0) := "1111";
    signal result : std_logic_vector (7 downto 0);
    signal flags : std_logic_vector (2 downto 0);   -- [S,OF,Z] 
begin

    process (operation) begin
        flags <= (others => '0');
        result <= (others => '0');
        case operation is
            when "000" => 
                result <= std_logic_vector((unsigned("0000"&A) + unsigned(B)));
                flags(1) <= result(4);
            when "001" =>
                if (A >= B) then
                    result <= std_logic_vector(unsigned("0000"&A) - unsigned(B));
                    flags(2) <= '0';
                else
                    result <= std_logic_vector(unsigned("0000"&B) - unsigned(A));
                    flags(2) <= '1';
                end if;
            when "010" =>
                result <= "0000"&A and "0000"&B;
            when "011" =>
                result <= "0000"&A or "0000"&B;
            when "100" =>
                result <= "0000"&A xor "0000"&B;
            when "101" =>
                result <= not ("1111"&A);
            when "110"  =>
                result <= not ("1111"&B);
            when "111" =>
                result <= std_logic_vector(unsigned(A) * unsigned(B));
            when others =>
                result <= (others => 'Z');
        end case;
    end process;

end Behavioral;

score 1 · Answer 1 · answered Nov 17 '11 at 13:09

1

The only way I can see all Us happening (with the code as is) is if the process never executes. Which means you must have no transactions on the operation signal for the add operation.

Which only raises more questions:

Are you definitely getting Us (not Xs maybe?): is something else driving the signal as well?

Can you post your testbench code?

answered Nov 17 '11 at 13:09

Martin Thompson

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Yep, completely sure they are U's. I'll post later the testbench code. Thanks for the help ! – BRabbit27 Nov 17 '11 at 23:46

score 0 · Answer 2 · answered Nov 17 '11 at 12:40

0

The first two things that come to mind looking at your code are:

You should include A and B in the process sensitivity list (now it only contains operation).
You can't use result(4) to set flags(1), as result(4) will only be updated after the process, and result itself isn't on the sensitivity list again so the process won't be triggered again to reflect the changed value. The best option is probably to store the sum in a variable, then assign that to result and the overflow bit.

answered Nov 17 '11 at 12:40

Tomi Junnila

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As Martin Thompson pointed out, if you get `UUUU` from `result`, then the process is never being executed, and thus my points above won't fix your issue (though I think they are problems you'll encounter once you fix the behaviour of your test bench). – Tomi Junnila Nov 17 '11 at 13:31

VHDL ALU undefined value

2 Answers2