generate condition in vhdl

Question

I have a shift register in my top module called Rrg and I want to instantiate Sbox module when Rrg(1) = '1' in the called EnCore module. I have warnings:

1)Condition in IF GENERATE must be static.

2)Uninitialized out port Do has no driver. This port will contribute value (U) to the signal network.

entity EncCore is
    port (
        di : in std_logic_vector(127 downto 0);
        Rrg : in std_logic_vector(4 downto 0);
        Do : out std_logic_vector(127 downto 0)
    );
end EncCore;

architecture behavioral of EncCore is
begin
gen : if (Rrg(1)='1') generate
            innergen : for i in 0 to 15 generate
            sbox_inst :  sbox
                port map(
                    input_byte  => di((i + 1)*8 - 1 downto i*8),
                    output_byte => Do((i + 1)*8 - 1 downto i*8)
                );      
            end generate innergen;
     end generate gen;
end architecture behavioral;

You probably want to make a multiplexer for non-static conditionals/gating etc (not use static compile time known condition for generate). Rrg(1) could be used as select between Do getting nothing/zeros vs the output_byte from sbox. — Julian Kemmerer, Aug 18 '23 at 15:24
yes. the Rrg is not static. With the current code, the Do signal is uninitialized and has no driver. how can I fix it? — ghazalia, Aug 18 '23 at 15:34
VHDL doesn't have modules, an entity and associated.architecture represent nested block statements when elaborated. An entity is an external block. An actual block statement is an internal block. Entities are not called, a design hierarchy is elaborated into a globally static collection of signal nets interconnecting processes. This is why generate conditions are required to be globally static (the definition embraces locally static as well). — user16145658, Aug 18 '23 at 19:30
Provide context, here the entities context clause with any library clauses and use clauses. Without a use clause making component sbox declaration visible you'd get another error. Provide a [mcve] that reproduces the two errors. The second error can then be explained and corrected. — user16145658, Aug 18 '23 at 19:34
search for duplicate questions, here for example the Related question on your question page [VHDL condition in if...](https://stackoverflow.com/questions/48060264/vhdl-condition-in-if-must-be-static-and-component-instantiation-inside-if-statem) — user16145658, Aug 18 '23 at 20:14

zeekay · Answer 1 · 2023-08-18T16:00:15.020

You cannot use IF..GENERATE for conditions, which shall be evaluated at run-time. IF..GENERATE (and FOR..GENERATE) are similar to the pre-processor instructions in C/C++. With these instructions you can direct, if some logic shall be included or to include it multiple times.

So these are compile-time instructions and therefore they have to be static (e.g. based on constants).

But there is a general problem with your code. You want to use the logic inside sbox only when Rrg(1)='1'. In software it is correct, to call a function only when its result is needed, but with a hardware description language like VHDL you have to think differently. It is not possible to change the hardware (or the FPGA configuration) during run-time, but the circuits for every part of your design has to be there right from the beginning, even if it shall be used only a single time during run-time.

In principle it would be sufficient to just remove the IF..GENERATE condition, but maybe you want to mask the output when it is not valid or to flag to the outside, when the output can be used. This depends on what is happening outside of your entity...

It's called a generate statement and it's a concurrent statement. The underlying issue here is the Op refers to the "called EnCore module" when a design is elaborated into a static design hierarchy of processes interconnected by signal nets consisting of drivers and ports. It's a hardware description and not a program by itself. The design model is statically linked to a simulation kernel which is the program. See for example IEEE Std 1076-2008 14. Elaboration and execution. — user16145658, Aug 18 '23 at 19:50
Concurrent statements represent processes and/or hierarchy in an elaborated design hierarchy. Procedure calls are statements and function calls are expressions. Sequential statements describe behavior (algorithms) and are found in processes and subprograms, procedures and functions which are dynamically elaborated (called). — user16145658, Aug 18 '23 at 20:03

generate condition in vhdl

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