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I have 2 blocks, out of which block_A is writing and block_B is reading.

Writing configurations : 3 writes per 5 clocks,
Reading configurations : 30 reads per 50 clocks

What is the required FIFO depth in order to avoid FIFO underflow/overflow? It is provided that both the FIFOs are working at same frequency.

IF we calculate the frequency then, it would be 3/5 for both the Blocks. But then again this frequency of 3/5 is an average frequency. So I am not sure how to calculate the FIFO depth.

toolic
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purval vikani
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1 Answers1

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It's not clear to me from your description if this a fixed pattern, or some estimation over a very long period of time for one of the sides.

If it's guaranteed that we will have 3 writes per 5 cycles, and 30 reads per 50 cycles, then you can calculate the needed buffer depth using the equation:

FifoDepth = BW*LatencyFromPushToPop

In your case:

BW = 3/5   //This is the BW that you want to pass through the FIFO. 
LatencyFromPushToPop = (50-30) = 20 cycles //you must add to this number the actual latency of the FIFO (1, 2 cycles?), which I am not considering here

From this equation you get that the minimal FIFO depth to avoid write backpressure, is:

 3 / 5 * 20 = 12.

You can also get to it by trying to simulate the worst case scenario of the FIFO fill level:

  1. Block B starts reading only after 20 cycles.
  2. Block A writes as much as it can during those 20 cycles.

Block A will write during 20 cycles at most 20 / 5 * 3 = 12 entries.

When block B will start reading it will read 30 entries straight. During those 30 cycles, block A will write at most 30 / 5 * 3 = extra 18 entries.

Since block B will read during those 30 cycles 30 entries, which are exactly 12+18 entries, the FIFO will be emptied and will not cross the number 12 in its fill level (and we are back to the square one).

Note1:

Not sure I understand what you mean by underflow. By definition block A sends data only 3/5 of the time, so there must be some cycles where there is nothing to read from the FIFO. If there is nothing to read from the FIFO, block B should not pop anything.

Note2:

If one of the sides average BW is an estimation over a long period of time, then it really depends on the burstiness of the traffic.

A good example for it is if a block writes 50% of the time over a period of 1 second, but writes everything during the first 0.5 second.

On average the write BW is 50%, but the FIFO needs to absorb 100% write traffic during the first 0.5 second. Therefore you must understand the patterns and the time frames to optimize the FIFO when using average BWs over long period of time.

EEliaz
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