Using System Verilog assertions for AXI

Question

I can't finish the code for this: AXI ARID for issuing multiple reads and device responds with data out of order with matching RID.

How can you check if master is reusing a ARID of an outstanding read.

I have started this way, I know I can save the outstanding rid in a Queue, then I can delete upon receiving the ack for that req, but not sure how to check. I am sure this is too rough, but I am new in SVA. I wish to know where to add the check for then new request ID, if I put the check in the antecedent then I might create vacuous pass.

int rid[$];
always @(posedge req) rid.push_back(RID_RTL);
always @(posedge ack) begin
 foreach(rid[i]) begin
  if(rid[i]== ACK_RID)
    rid[i].delete();
 end
end
property REQACK_P;
  @(posedge clk) disable iff(!rst_n) 
  $rose(req) |=> ##[0:$]  $rose(ack);
endproperty

Parth Pandya · Answer 1 · 2023-08-25T21:00:02.780

-1

you can define associative array for rid and then use inbuilt method "exists". For every request it makes flag=1 for corresponding arid and whenever ack is received , it clears the flag. So, associative array represents outstanding read requests.

If you want to count outstanding request you can make array as "int rid_a[int]" and increment/decrement as per req/ack.

bit rid_a[int];
always @(posedge req) 
begin
  assert(!rid_a.exists(req.arid))
  rid_a[arid]=1; 
always @(posedge ack)
begin
  rid_a[rid]=0;
end

edited Aug 25 '23 at 21:00

answered Aug 16 '23 at 21:31

Parth Pandya

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1
5

Thanks, I see this will work. Of course there needs to be some initial code where we are storing the RID before checking it, right? I can't quite see the full picture. How would we store and why are you assigning 1 at the ACK phase? – George K Aug 24 '23 at 22:49
updated description and code for checking outstanding arid. – Parth Pandya Aug 25 '23 at 21:01

Using System Verilog assertions for AXI

1 Answers1