I learned that every core in RISC-V can handle an interrupt. So when one core is running in u-mode, will it trap into s-mode and handle the interrupt? Or only in s-mode core can handle this interrupt?
I tried debug xv6 os, seems like every uart interrupt is trapped from s-mode (result show on backtrace is kernelvec)
To be short, the question is: when will an interrupt be handled, assume core is in x-mode and interrupt is a y-mode interrupt?
