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I'm currently working on modeling a basic/symmetrical charge pump in Verilog-A for the z domain. However, I'm encountering a discrepancy between the results obtained from the Verilog-A model and the schematic. I would like the Verilog-A model to closely resemble the behavior of the schematic model, particularly with respect to the steps observed in the output.

If anyone has experience with this issue or knows how to achieve the desired behavior in the Verilog-A model, I would greatly appreciate your assistance. Thank you in advance for your help!

Need help aligning Verilog-A charge pump model with schematic for desired output behavior enter image description here

toolic
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wiss jl
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    I think that [tag:verilog] is more for digital logic. You should note verilog-AMS or express that you are using 'analog' verilog. You could try to zero in on aspects of the design where the simulations differ. Ie, ripple , etc. Also, even straight verilog seems to be more active on the [electronics site](https://electronics.stackexchange.com/questions/tagged/verilog-a). – artless noise Jul 05 '23 at 20:27

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