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This is a Block Design in Xilinx Vivado on Arty A7-100T FPGA Development Board. Everything works well if I use a common clock port that is specified in Arty-A7-100-Master.xdc:

## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { sys_clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { sys_clk_i }];

An ILA debugging window is shown after programming.

Now I wanna use the System Clock board component on the A7-100T board. This is specified in board file board.xml:

  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
    <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
  </component>

and can be seen in Board tab of Xilinx Vivado: enter image description here

I took pains to add this System Clock into the Block Design diagram, but after successful bitstream generation, I encountered an error saying the debug hub core was not detected when programming the FPGA device:

program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'design_1_i/system_ila_0/inst/ila_lib' at location 'uuid_CD4C83C823A6596D99AD09BE1335C6B0' from probes file, since it cannot be found on the programmed device.

The ILA debugging window does not show.

The method I add the System Clock component is as follows:

  1. I drag-and drop the System Clock component from the Board tab in Vivado into the Block Design diagram. Vivado gives it a name "sys_clock", exactly the same as the one in the board file. I then connect sys_clock to the needed part of the design.
  2. Vivado forces adding a Clocking Wizard. If I delete it, sys_clock will be a common clock port, returning to the original design. But I want to use System Clock board component, so I have to keep this IP: enter image description here
  3. I add command set_property SEVERITY {Warning} [get_drc_checks UCIO-1] in the Arty-A7-100-Master.xdc to avoid the error saying I should specify physical FPGA pin to sys_clock.
  4. I run the "Set Up Debug" wizard in Synthesized Design and leave everything by default. The wizard add the following stuff in Arty-A7-100-Master.xdc:
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list design_1_i/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {design_1_i/axi_dma_0_M_AXI_MM2S_ARBURST[0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {design_1_i/axi_dma_0_M_AXI_S2MM_AWBURST[0]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
  1. I go through Run Implementation and Generate Bitstream and encountered the above error when programming the board.

So my question is:

  1. I tried my best to go through the workflow in Vivado to use the System Clock board component without any assistance. Is the method correct? If my method of adding System Clock is incorrect which causes the error, please let me know. I think there should be something wrong because the steps are so awkward, completely unlike another board component System Reset which is so easy to use.
  2. If my addition is correct, how to fix the issue of not detecting the debugging core?

I'm using Xilinx Vivado 2023.1 on Windows 10.

Below is what I have done to try to solve the problem:

I searched Internet but cannot find any solution. For example this one which is inapplicable. I believe the clock connection is correct because the design works well with common clock port and I did not change anything other than the System Clock. If I open the implemented design and run get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub] as suggested by the error message, the command returns 1, which I guess means the debug core does exist. But it just cannot be detected.

halfer
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zzzhhh
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  • You said you needed to adjust severity 'avoid the error saying I should specify physical FPGA pin to sys_clock.' That sounds like somewhere the tool is confused about which pin sys clock should come from. Can you confirm your clock signal is working correctly by like blinking an led to check? The ILA core might not show up if its clock isnt running. Can you do a similar check trying to blink an LED using that other clock that ILA says its using, that ...design_1_i/mig_7series_0... / u_bufg_clkdiv0_0 clock, looks like clock generated by the memory controller - maybe make sure that is reset? – Julian Kemmerer Jun 27 '23 at 14:12
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    hi, Julian, Thank you so much for the comment. It is very helpful and inspiring. I was out of town yesterday so I couldn't do the real implementation and experiment, but that gave me a chance to take some while to deeply think about your comment, and I finally figured it out. The issue comes from I assuming Vivado connects the System Clock automatically (and correctly). After synthesis, I go to I/O Ports tab and find that the System Clock is indeed unconnected. Then I set the clock to E3 as indicated in the xdc file, reload, force synthesis as up-to-date and proceed with the remaining steps... – zzzhhh Jun 29 '23 at 00:58
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    ...in Vivado workflow, and everything works as expected. The ILA debug window shows up. Thank you so much again for the helpful and inspiring comment. As a side note, although I use the word "assume", it does not mean my assumption is incorrect. Vivado does connect System Clock automatically, but only if I do it in a way Vivado accepts it. In other words, it works sometimes, but does not work some other time. I'm really frustrated by such a fragile behavior of Vivado. I respond late also partly because I'm trying to get a consistent result. Anyway, at least I know what the correct approach is. – zzzhhh Jun 29 '23 at 01:08

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