always @(clk) begin #10 clk <= ~clk;end //works
always @(clk) begin #10 clk = ~clk;end //doesn't work
Works means execution re-enters the always block, behaves like a oscillator.
Does not work mean it execute only once.
I've read Scheduling semantics part in Verilog Standard, as I understand it now, in a time step, all statements in the process are placed in the hierarchical event queue at the same time, until the process is suspended when the timing control statement in the process is encountered. The statements are then sorted and sorted. If the statements are in a begin end block, the statements need to be sorted in the order in which they appear.
As I understand it, both blocking and non-blocking assignments can generate a flapping clock because the timing control statement in the process is detected before the assignment is updated.
Is the evaluation of events in a time step done sentence by sentence? Or there's something wrong with my understanding.
Why can a non-blocking update event trigger a sensitive event at the same time step? Could You tell me how evaluation and update events enter the hierarchical event queue?