What is the value inside pinctrl

Question

I am working on a board based on iMX8MP processor. I was looking at device tree source and there are a lot of pin muxing. For instance :

pinctrl_keys: keysgrp {
    fsl,pins = <
        MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13         0x00000140
        MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03          0x00000140
        MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04          0x00000140
        MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23         0x00000140
    >;
};

My question is: from where the value 0x00000140 came from ? What does it mean. I looked inside the iMX8MP reference manual but no information explain that value.

According to https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/fsl%2Cimx8mp-pinctrl.yaml the last number is the "pad setting" value. It says "Please refer to i.MX8M Plus Reference Manual for detailed CONFIG settings". It seems that a login is required to access that manual and I couldn't be bothered creating an account just to download the manual. — Ian Abbott, May 03 '23 at 17:29

score 2 · Accepted Answer · edited May 09 '23 at 20:55

The documentation for the imx8mp pinctrl device tree bindings is Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml. Here it describes the fsl,pins property as:

properties:
  fsl,pins:
    description:
      each entry consists of 6 integers and represents the mux and config
      setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
      mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
      be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
      integer CONFIG is the pad setting value like pull-up on this pin. Please
      refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      items:
        - description: |
            "mux_reg" indicates the offset of mux register.
        - description: |
            "conf_reg" indicates the offset of pad configuration register.
        - description: |
            "input_reg" indicates the offset of select input register.
        - description: |
            "mux_val" indicates the mux value to be applied.
        - description: |
            "input_val" indicates the select input value to be applied.
        - description: |
            "pad_setting" indicates the pad configuration value to be applied.

If we take your example, MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 is defined in arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h as

#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13    0x17C 0x3DC 0x000 0x5 0x0

So the pad configuration register offset is 0x3DC. If we look at the i.MX8M Plus Applications Processor Reference Manual, the register at offset 0x3DC in the IOMUX Controller (IOMUXC) is SW_PAD_CTL_PAD_SAI1_TXD1 SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1):

Field	Description
8 PE	Pull Select Field Select one out of next values for pad: SAI1_TXD1 0 PE_0_PULL_DISABLE — Pull Disable 1 PE_1_PULL_ENABLE — Pull Enable
7 HYS	Input Select Field Select one out of next values for pad: SAI1_TXD1 0 HYS_0_CMOS — CMOS 1 HYS_1_SCHMITT — Schmitt
6 PUE	Pull Up / Down Config. Field Select one out of next values for pad: SAI1_TXD1 0 PUE_0_WEAK_PULL_DOWN — Weak pull down 1 PUE_1_WEAK_PULL_UP — Weak pull up
5 ODE	Open Drain Field Select one out of next values for pad: SAI1_TXD1 0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable 1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 FSEL	Slew Rate Field Select one out of next values for pad: SAI1_TXD1 0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1) 1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 -	This field is reserved. Reserved
2–1 DSE	Drive Strength Field Select one out of next values for pad: SAI1_TXD1 00 DSE_X1 — X1 10 DSE_X2 — X2 01 DSE_X4 — X4 11 DSE_X6 — X6
0 -	This field is reserved. Reserved

A pad configuration value of 0x140 is enabling the pull up, and disabling the Schmitt trigger. The other settings are irrelevant as this is an input pin.

What is the value inside pinctrl

1 Answers1